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Merge tag 'mediatek-drm-next-20251120' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next

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Mediatek DRM Next - 20251120

1. Fix probe resource leaks
2. Add support for MT8195/88 HDMIv2 and DDCv2
3. Fix CCORR mtk_ctm_s31_32_to_s1_n function issue
4. Fix device node reference leak in mtk_dp_dt_parse()

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patch.msgid.link/20251119233202.10034-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie
2025-11-21 18:48:20 +10:00
parent ee31621316 a846505a19
commit 611d4d1606
14 changed files with 2925 additions and 549 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/gpu/drm/mediatek/Kconfig
View File

@@ -30,9 +30,30 @@ config DRM_MEDIATEK_DP
help
DRM/KMS Display Port driver for MediaTek SoCs.
config DRM_MEDIATEK_HDMI_COMMON
tristate
depends on DRM_MEDIATEK
select DRM_DISPLAY_HDMI_HELPER
select DRM_DISPLAY_HELPER
select SND_SOC_HDMI_CODEC if SND_SOC
help
MediaTek SoC HDMI common library
config DRM_MEDIATEK_HDMI
tristate "DRM HDMI Support for Mediatek SoCs"
depends on DRM_MEDIATEK
select SND_SOC_HDMI_CODEC if SND_SOC
select DRM_MEDIATEK_HDMI_COMMON
help
DRM/KMS HDMI driver for Mediatek SoCs
config DRM_MEDIATEK_HDMI_V2
tristate "DRM HDMI v2 IP support for MediaTek SoCs"
depends on DRM_MEDIATEK
select DRM_MEDIATEK_HDMI_COMMON
help
Say yes here to enable support for the HDMIv2 IP and related
DDCv2 as found in the MediaTek MT8195, MT8188 SoCs and other
variants.
This driver can also be built as a module. If so, the HDMIv2
module will be called "mtk_hdmi_v2", and the DDCv2 module
will be called "mtk_hdmi_ddc_v2".

3
drivers/gpu/drm/mediatek/Makefile
View File

@@ -21,8 +21,11 @@ mediatek-drm-y := mtk_crtc.o \
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_cec.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mtk_hdmi_ddc.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mtk_hdmi_v2.o
obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mtk_hdmi_ddc_v2.o
obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o

33
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
View File

@@ -621,15 +621,27 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
return ret;
}
int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
static void mtk_ddp_comp_put_device(void *_dev)
{
struct device *dev = _dev;
put_device(dev);
}
static void mtk_ddp_comp_clk_put(void *_clk)
{
struct clk *clk = _clk;
clk_put(clk);
}
int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_ddp_comp *comp,
unsigned int comp_id)
{
struct platform_device *comp_pdev;
enum mtk_ddp_comp_type type;
struct mtk_ddp_comp_dev *priv;
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
int ret;
#endif
if (comp_id >= DDP_COMPONENT_DRM_ID_MAX)
return -EINVAL;
@@ -651,6 +663,10 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
}
comp->dev = &comp_pdev->dev;
ret = devm_add_action_or_reset(dev, mtk_ddp_comp_put_device, comp->dev);
if (ret)
return ret;
if (type == MTK_DISP_AAL ||
type == MTK_DISP_BLS ||
type == MTK_DISP_CCORR ||
@@ -666,15 +682,22 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DSI)
return 0;
priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->regs = of_iomap(node, 0);
priv->regs = devm_of_iomap(dev, node, 0, NULL);
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
priv->clk = of_clk_get(node, 0);
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
ret = devm_add_action_or_reset(dev, mtk_ddp_comp_clk_put, priv->clk);
if (ret)
return ret;
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
if (ret)

2
drivers/gpu/drm/mediatek/mtk_ddp_comp.h
View File

@@ -350,7 +350,7 @@ static inline void mtk_ddp_comp_encoder_index_set(struct mtk_ddp_comp *comp)
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev);
int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp,
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, struct mtk_ddp_comp *comp,
unsigned int comp_id);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id);
void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,

23
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
View File

@@ -80,27 +80,6 @@ void mtk_ccorr_stop(struct device *dev)
writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
}
/* Converts a DRM S31.32 value to the HW S1.n format. */
static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
{
u16 r;
/* Sign bit. */
r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
if ((in & GENMASK_ULL(62, 33)) > 0) {
/* identity value 0x100000000 -> 0x400(mt8183), */
/* identity value 0x100000000 -> 0x800(mt8192), */
/* if bigger this, set it to max 0x7ff. */
r |= GENMASK(n, 0);
} else {
/* take the n+1 most important bits. */
r |= (in >> (32 - n)) & GENMASK(n, 0);
}
return r;
}
void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
{
struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
@@ -119,7 +98,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
input = ctm->matrix;
for (i = 0; i < ARRAY_SIZE(coeffs); i++)
coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
coeffs[i] = drm_color_ctm_s31_32_to_qm_n(input[i], 2, matrix_bits);
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
&ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);

12
drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
View File

@@ -527,6 +527,13 @@ bool mtk_ovl_adaptor_is_comp_present(struct device_node *node)
type == OVL_ADAPTOR_TYPE_PADDING;
}
static void ovl_adaptor_put_device(void *_dev)
{
struct device *dev = _dev;
put_device(dev);
}
static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match)
{
struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
@@ -560,6 +567,11 @@ static int ovl_adaptor_comp_init(struct device *dev, struct component_match **ma
if (!comp_pdev)
return -EPROBE_DEFER;
ret = devm_add_action_or_reset(dev, ovl_adaptor_put_device,
&comp_pdev->dev);
if (ret)
return ret;
priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
drm_of_component_match_add(dev, match, component_compare_of, node);

1
drivers/gpu/drm/mediatek/mtk_dp.c
View File

@@ -2087,6 +2087,7 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,
endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 1, -1);
len = of_property_count_elems_of_size(endpoint,
"data-lanes", sizeof(u32));
of_node_put(endpoint);
if (len < 0 || len > 4 || len == 3) {
dev_err(dev, "invalid data lane size: %d\n", len);
return -EINVAL;

4
drivers/gpu/drm/mediatek/mtk_drm_drv.c
View File

@@ -1123,7 +1123,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
(void *)private->mmsys_dev,
sizeof(*private->mmsys_dev));
private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
mtk_ddp_comp_init(dev, NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
DDP_COMPONENT_DRM_OVL_ADAPTOR);
component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
}
@@ -1189,7 +1189,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
node);
}
ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
ret = mtk_ddp_comp_init(dev, node, &private->ddp_comp[comp_id], comp_id);
if (ret) {
of_node_put(node);
goto err_node;

539
drivers/gpu/drm/mediatek/mtk_hdmi.c
View File

@@ -31,6 +31,7 @@
#include <drm/drm_probe_helper.h>
#include "mtk_cec.h"
#include "mtk_hdmi_common.h"
#include "mtk_hdmi_regs.h"
#define NCTS_BYTES 7
@@ -43,143 +44,6 @@ enum mtk_hdmi_clk_id {
MTK_HDMI_CLK_COUNT
};
enum hdmi_aud_input_type {
HDMI_AUD_INPUT_I2S = 0,
HDMI_AUD_INPUT_SPDIF,
};
enum hdmi_aud_i2s_fmt {
HDMI_I2S_MODE_RJT_24BIT = 0,
HDMI_I2S_MODE_RJT_16BIT,
HDMI_I2S_MODE_LJT_24BIT,
HDMI_I2S_MODE_LJT_16BIT,
HDMI_I2S_MODE_I2S_24BIT,
HDMI_I2S_MODE_I2S_16BIT
};
enum hdmi_aud_mclk {
HDMI_AUD_MCLK_128FS,
HDMI_AUD_MCLK_192FS,
HDMI_AUD_MCLK_256FS,
HDMI_AUD_MCLK_384FS,
HDMI_AUD_MCLK_512FS,
HDMI_AUD_MCLK_768FS,
HDMI_AUD_MCLK_1152FS,
};
enum hdmi_aud_channel_type {
HDMI_AUD_CHAN_TYPE_1_0 = 0,
HDMI_AUD_CHAN_TYPE_1_1,
HDMI_AUD_CHAN_TYPE_2_0,
HDMI_AUD_CHAN_TYPE_2_1,
HDMI_AUD_CHAN_TYPE_3_0,
HDMI_AUD_CHAN_TYPE_3_1,
HDMI_AUD_CHAN_TYPE_4_0,
HDMI_AUD_CHAN_TYPE_4_1,
HDMI_AUD_CHAN_TYPE_5_0,
HDMI_AUD_CHAN_TYPE_5_1,
HDMI_AUD_CHAN_TYPE_6_0,
HDMI_AUD_CHAN_TYPE_6_1,
HDMI_AUD_CHAN_TYPE_7_0,
HDMI_AUD_CHAN_TYPE_7_1,
HDMI_AUD_CHAN_TYPE_3_0_LRS,
HDMI_AUD_CHAN_TYPE_3_1_LRS,
HDMI_AUD_CHAN_TYPE_4_0_CLRS,
HDMI_AUD_CHAN_TYPE_4_1_CLRS,
HDMI_AUD_CHAN_TYPE_6_1_CS,
HDMI_AUD_CHAN_TYPE_6_1_CH,
HDMI_AUD_CHAN_TYPE_6_1_OH,
HDMI_AUD_CHAN_TYPE_6_1_CHR,
HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
HDMI_AUD_CHAN_TYPE_6_0_CS,
HDMI_AUD_CHAN_TYPE_6_0_CH,
HDMI_AUD_CHAN_TYPE_6_0_OH,
HDMI_AUD_CHAN_TYPE_6_0_CHR,
HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
};
enum hdmi_aud_channel_swap_type {
HDMI_AUD_SWAP_LR,
HDMI_AUD_SWAP_LFE_CC,
HDMI_AUD_SWAP_LSRS,
HDMI_AUD_SWAP_RLS_RRS,
HDMI_AUD_SWAP_LR_STATUS,
};
struct hdmi_audio_param {
enum hdmi_audio_coding_type aud_codec;
enum hdmi_audio_sample_size aud_sample_size;
enum hdmi_aud_input_type aud_input_type;
enum hdmi_aud_i2s_fmt aud_i2s_fmt;
enum hdmi_aud_mclk aud_mclk;
enum hdmi_aud_channel_type aud_input_chan_type;
struct hdmi_codec_params codec_params;
};
struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
unsigned long max_mode_clock;
};
struct mtk_hdmi {
struct drm_bridge bridge;
struct drm_bridge *next_bridge;
struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
struct device *dev;
const struct mtk_hdmi_conf *conf;
struct phy *phy;
struct device *cec_dev;
struct i2c_adapter *ddc_adpt;
struct clk *clk[MTK_HDMI_CLK_COUNT];
struct drm_display_mode mode;
bool dvi_mode;
struct regmap *sys_regmap;
unsigned int sys_offset;
struct regmap *regs;
struct platform_device *audio_pdev;
struct hdmi_audio_param aud_param;
bool audio_enable;
bool powered;
bool enabled;
hdmi_codec_plugged_cb plugged_cb;
struct device *codec_dev;
struct mutex update_plugged_status_lock;
};
static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
{
return container_of(b, struct mtk_hdmi, bridge);
}
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
{
regmap_update_bits(hdmi->regs, VIDEO_CFG_4,
@@ -600,88 +464,6 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
regmap_write(hdmi->regs, GRL_CFG5, val);
}
struct hdmi_acr_n {
unsigned int clock;
unsigned int n[3];
};
/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
static const struct hdmi_acr_n hdmi_rec_n_table[] = {
/* Clock, N: 32kHz 44.1kHz 48kHz */
{ 25175, { 4576, 7007, 6864 } },
{ 74176, { 11648, 17836, 11648 } },
{ 148352, { 11648, 8918, 5824 } },
{ 296703, { 5824, 4459, 5824 } },
{ 297000, { 3072, 4704, 5120 } },
{ 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
};
/**
* hdmi_recommended_n() - Return N value recommended by HDMI specification
* @freq: audio sample rate in Hz
* @clock: rounded TMDS clock in kHz
*/
static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
{
const struct hdmi_acr_n *recommended;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
if (clock == hdmi_rec_n_table[i].clock)
break;
}
recommended = hdmi_rec_n_table + i;
switch (freq) {
case 32000:
return recommended->n[0];
case 44100:
return recommended->n[1];
case 48000:
return recommended->n[2];
case 88200:
return recommended->n[1] * 2;
case 96000:
return recommended->n[2] * 2;
case 176400:
return recommended->n[1] * 4;
case 192000:
return recommended->n[2] * 4;
default:
return (128 * freq) / 1000;
}
}
static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
{
switch (clock) {
case 25175:
return 25174825; /* 25.2/1.001 MHz */
case 74176:
return 74175824; /* 74.25/1.001 MHz */
case 148352:
return 148351648; /* 148.5/1.001 MHz */
case 296703:
return 296703297; /* 297/1.001 MHz */
default:
return clock * 1000;
}
}
static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
unsigned int tmds_clock, unsigned int n)
{
return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
128 * audio_sample_rate);
}
static void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
unsigned int *n, unsigned int *cts)
{
*n = hdmi_recommended_n(sample_rate, clock);
*cts = hdmi_expected_cts(sample_rate, clock, *n);
}
static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
unsigned int cts)
{
@@ -1072,20 +854,6 @@ static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
[MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
};
static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
struct device_node *np)
{
int i;
for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
hdmi->clk[i] = of_clk_get_by_name(np,
mtk_hdmi_clk_names[i]);
if (IS_ERR(hdmi->clk[i]))
return PTR_ERR(hdmi->clk[i]);
}
return 0;
}
static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
{
int ret;
@@ -1230,13 +998,6 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
return 0;
}
static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
return true;
}
static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_atomic_state *state)
{
@@ -1268,28 +1029,6 @@ static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
hdmi->powered = false;
}
static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
adjusted_mode->name, adjusted_mode->hdisplay);
dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
adjusted_mode->hsync_start, adjusted_mode->hsync_end,
adjusted_mode->htotal);
dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
adjusted_mode->hskew, adjusted_mode->vdisplay);
dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
adjusted_mode->vsync_start, adjusted_mode->vsync_end,
adjusted_mode->vtotal);
dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
adjusted_mode->vscan, adjusted_mode->flags);
drm_mode_copy(&hdmi->mode, adjusted_mode);
}
static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_atomic_state *state)
{
@@ -1345,169 +1084,10 @@ static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
.edid_read = mtk_hdmi_bridge_edid_read,
};
static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
{
struct platform_device *cec_pdev;
struct device_node *cec_np;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
if (ret)
return dev_err_probe(dev, ret, "Failed to get clocks\n");
/* The CEC module handles HDMI hotplug detection */
cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
if (!cec_np)
return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
cec_pdev = of_find_device_by_node(cec_np);
if (!cec_pdev) {
dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
cec_np);
of_node_put(cec_np);
return -EPROBE_DEFER;
}
of_node_put(cec_np);
/*
* The mediatek,syscon-hdmi property contains a phandle link to the
* MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
* registers it contains.
*/
hdmi->sys_regmap = syscon_regmap_lookup_by_phandle_args(np, "mediatek,syscon-hdmi",
1, &hdmi->sys_offset);
if (IS_ERR(hdmi->sys_regmap))
return dev_err_probe(dev, PTR_ERR(hdmi->sys_regmap),
"Failed to get system configuration registers\n");
hdmi->cec_dev = &cec_pdev->dev;
return 0;
}
static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *remote, *i2c_np;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
if (ret)
return dev_err_probe(dev, ret, "Failed to get clocks\n");
hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs))
return PTR_ERR(hdmi->regs);
remote = of_graph_get_remote_node(np, 1, 0);
if (!remote)
return -EINVAL;
if (!of_device_is_compatible(remote, "hdmi-connector")) {
hdmi->next_bridge = of_drm_find_bridge(remote);
if (!hdmi->next_bridge) {
dev_err(dev, "Waiting for external bridge\n");
of_node_put(remote);
return -EPROBE_DEFER;
}
}
i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
of_node_put(remote);
if (!i2c_np)
return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
of_node_put(i2c_np);
if (!hdmi->ddc_adpt)
return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
if (ret)
return ret;
return 0;
}
/*
* HDMI audio codec callbacks
*/
static int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
struct hdmi_codec_daifmt *daifmt,
struct hdmi_codec_params *params)
{
struct hdmi_audio_param aud_params = { 0 };
unsigned int chan = params->cea.channels;
dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
params->sample_rate, params->sample_width, chan);
if (!hdmi->bridge.encoder)
return -ENODEV;
switch (chan) {
case 2:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
break;
case 4:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
break;
case 6:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
break;
case 8:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
break;
default:
dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
return -EINVAL;
}
switch (params->sample_rate) {
case 32000:
case 44100:
case 48000:
case 88200:
case 96000:
case 176400:
case 192000:
break;
default:
dev_err(hdmi->dev, "rate[%d] not supported!\n",
params->sample_rate);
return -EINVAL;
}
switch (daifmt->fmt) {
case HDMI_I2S:
aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
break;
case HDMI_SPDIF:
aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
break;
default:
dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
daifmt->fmt);
return -EINVAL;
}
memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
aud_params.aud_codec, aud_params.aud_input_type,
aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
return 0;
}
static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
struct hdmi_codec_daifmt *daifmt,
struct hdmi_codec_params *params)
@@ -1555,26 +1135,6 @@ mtk_hdmi_audio_mute(struct device *dev, void *data,
return 0;
}
static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
if (hdmi->enabled)
memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
else
memset(buf, 0, len);
return 0;
}
static void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
struct device *codec_dev)
{
mutex_lock(&hdmi->update_plugged_status_lock);
hdmi->plugged_cb = fn;
hdmi->codec_dev = codec_dev;
mutex_unlock(&hdmi->update_plugged_status_lock);
}
static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
hdmi_codec_plugged_cb fn,
struct device *codec_dev)
@@ -1596,92 +1156,21 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
.hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
};
static void mtk_hdmi_unregister_audio_driver(void *data)
{
platform_device_unregister(data);
}
static int mtk_hdmi_register_audio_driver(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
struct hdmi_audio_param *aud_param = &hdmi->aud_param;
struct hdmi_codec_pdata codec_data = {
.ops = &mtk_hdmi_audio_codec_ops,
.max_i2s_channels = 2,
.i2s = 1,
.data = hdmi,
.no_capture_mute = 1,
};
int ret;
aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
hdmi->audio_pdev = platform_device_register_data(dev,
HDMI_CODEC_DRV_NAME,
PLATFORM_DEVID_AUTO,
&codec_data,
sizeof(codec_data));
if (IS_ERR(hdmi->audio_pdev))
return PTR_ERR(hdmi->audio_pdev);
ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
hdmi->audio_pdev);
if (ret)
return ret;
return 0;
}
static int mtk_hdmi_probe(struct platform_device *pdev)
{
struct mtk_hdmi *hdmi;
struct device *dev = &pdev->dev;
int ret;
hdmi = devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge,
&mtk_hdmi_bridge_funcs);
hdmi = mtk_hdmi_common_probe(pdev);
if (IS_ERR(hdmi))
return PTR_ERR(hdmi);
hdmi->dev = dev;
hdmi->conf = of_device_get_match_data(dev);
ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
if (ret)
return ret;
hdmi->phy = devm_phy_get(dev, "hdmi");
if (IS_ERR(hdmi->phy))
return dev_err_probe(dev, PTR_ERR(hdmi->phy),
"Failed to get HDMI PHY\n");
mutex_init(&hdmi->update_plugged_status_lock);
platform_set_drvdata(pdev, hdmi);
ret = mtk_hdmi_register_audio_driver(dev);
if (ret)
return dev_err_probe(dev, ret,
"Failed to register audio driver\n");
hdmi->bridge.of_node = pdev->dev.of_node;
hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
hdmi->bridge.vendor = "MediaTek";
hdmi->bridge.product = "On-Chip HDMI";
ret = devm_drm_bridge_add(dev, &hdmi->bridge);
if (ret)
return dev_err_probe(dev, ret, "Failed to add bridge\n");
if (!hdmi->cec_dev)
return dev_err_probe(hdmi->dev, -ENODEV, "CEC is required by HDMIv1\n");
ret = mtk_hdmi_clk_enable_audio(hdmi);
if (ret)
return dev_err_probe(dev, ret,
return dev_err_probe(hdmi->dev, ret,
"Failed to enable audio clocks\n");
return 0;
@@ -1712,19 +1201,32 @@ static __maybe_unused int mtk_hdmi_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
static const struct mtk_hdmi_ver_conf mtk_hdmi_v1_ver_conf = {
.bridge_funcs = &mtk_hdmi_bridge_funcs,
.codec_ops = &mtk_hdmi_audio_codec_ops,
.mtk_hdmi_clock_names = mtk_hdmi_clk_names,
.num_clocks = ARRAY_SIZE(mtk_hdmi_clk_names)
};
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
.tz_disabled = true,
.ver_conf = &mtk_hdmi_v1_ver_conf
};
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
.max_mode_clock = 148500,
.cea_modes_only = true,
.max_mode_clock = 148500,
.ver_conf = &mtk_hdmi_v1_ver_conf
};
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8173 = {
.ver_conf = &mtk_hdmi_v1_ver_conf
};
static const struct of_device_id mtk_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
{ .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
{ .compatible = "mediatek,mt8173-hdmi" },
{ .compatible = "mediatek,mt8173-hdmi", .data = &mtk_hdmi_conf_mt8173 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
@@ -1744,3 +1246,4 @@ MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMI Driver");
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS("DRM_MTK_HDMI_V1");
MODULE_IMPORT_NS("DRM_MTK_HDMI");

456
drivers/gpu/drm/mediatek/mtk_hdmi_common.c Normal file
View File

@@ -0,0 +1,456 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Copyright (c) 2024 Collabora Ltd.
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include <drm/drm_modes.h>
#include <linux/device.h>
#include <linux/hdmi.h>
#include <linux/i2c.h>
#include <linux/math.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <sound/hdmi-codec.h>
#include "mtk_hdmi_common.h"
struct hdmi_acr_n {
unsigned int clock;
unsigned int n[3];
};
/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
static const struct hdmi_acr_n hdmi_rec_n_table[] = {
/* Clock, N: 32kHz 44.1kHz 48kHz */
{ 25175, { 4576, 7007, 6864 } },
{ 74176, { 11648, 17836, 11648 } },
{ 148352, { 11648, 8918, 5824 } },
{ 296703, { 5824, 4459, 5824 } },
{ 297000, { 3072, 4704, 5120 } },
{ 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
};
/**
* hdmi_recommended_n() - Return N value recommended by HDMI specification
* @freq: audio sample rate in Hz
* @clock: rounded TMDS clock in kHz
*/
static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
{
const struct hdmi_acr_n *recommended;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
if (clock == hdmi_rec_n_table[i].clock)
break;
}
recommended = hdmi_rec_n_table + i;
switch (freq) {
case 32000:
return recommended->n[0];
case 44100:
return recommended->n[1];
case 48000:
return recommended->n[2];
case 88200:
return recommended->n[1] * 2;
case 96000:
return recommended->n[2] * 2;
case 176400:
return recommended->n[1] * 4;
case 192000:
return recommended->n[2] * 4;
default:
return (128 * freq) / 1000;
}
}
static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
{
switch (clock) {
case 25175:
return 25174825; /* 25.2/1.001 MHz */
case 74176:
return 74175824; /* 74.25/1.001 MHz */
case 148352:
return 148351648; /* 148.5/1.001 MHz */
case 296703:
return 296703297; /* 297/1.001 MHz */
default:
return clock * 1000;
}
}
static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
unsigned int tmds_clock, unsigned int n)
{
return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
128 * audio_sample_rate);
}
void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
unsigned int *n, unsigned int *cts)
{
*n = hdmi_recommended_n(sample_rate, clock);
*cts = hdmi_expected_cts(sample_rate, clock, *n);
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_get_ncts, "DRM_MTK_HDMI");
int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
struct hdmi_codec_daifmt *daifmt,
struct hdmi_codec_params *params)
{
struct hdmi_audio_param aud_params = { 0 };
unsigned int chan = params->cea.channels;
dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
params->sample_rate, params->sample_width, chan);
if (!hdmi->bridge.encoder)
return -ENODEV;
switch (chan) {
case 2:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
break;
case 4:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
break;
case 6:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
break;
case 8:
aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
break;
default:
dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
return -EINVAL;
}
switch (params->sample_rate) {
case 32000:
case 44100:
case 48000:
case 88200:
case 96000:
case 176400:
case 192000:
break;
default:
dev_err(hdmi->dev, "rate[%d] not supported!\n",
params->sample_rate);
return -EINVAL;
}
switch (daifmt->fmt) {
case HDMI_I2S:
aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
break;
case HDMI_SPDIF:
aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
break;
default:
dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
daifmt->fmt);
return -EINVAL;
}
memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
aud_params.aud_codec, aud_params.aud_input_type,
aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
return 0;
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_params, "DRM_MTK_HDMI");
int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
if (hdmi->enabled)
memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
else
memset(buf, 0, len);
return 0;
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_get_eld, "DRM_MTK_HDMI");
void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
struct device *codec_dev)
{
mutex_lock(&hdmi->update_plugged_status_lock);
hdmi->plugged_cb = fn;
hdmi->codec_dev = codec_dev;
mutex_unlock(&hdmi->update_plugged_status_lock);
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_audio_set_plugged_cb, "DRM_MTK_HDMI");
static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node *np,
const char * const *clock_names, size_t num_clocks)
{
int i;
for (i = 0; i < num_clocks; i++) {
hdmi->clk[i] = of_clk_get_by_name(np, clock_names[i]);
if (IS_ERR(hdmi->clk[i]))
return PTR_ERR(hdmi->clk[i]);
}
return 0;
}
bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
return true;
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_bridge_mode_fixup, "DRM_MTK_HDMI");
void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode)
{
struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
adjusted_mode->name, adjusted_mode->hdisplay);
dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
adjusted_mode->hsync_start, adjusted_mode->hsync_end,
adjusted_mode->htotal);
dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
adjusted_mode->hskew, adjusted_mode->vdisplay);
dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
adjusted_mode->vsync_start, adjusted_mode->vsync_end,
adjusted_mode->vtotal);
dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
adjusted_mode->vscan, adjusted_mode->flags);
drm_mode_copy(&hdmi->mode, adjusted_mode);
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_bridge_mode_set, "DRM_MTK_HDMI");
static void mtk_hdmi_put_device(void *_dev)
{
struct device *dev = _dev;
put_device(dev);
}
static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
{
struct platform_device *cec_pdev;
struct device_node *cec_np;
int ret;
/* The CEC module handles HDMI hotplug detection */
cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
if (!cec_np)
return dev_err_probe(dev, -EOPNOTSUPP, "Failed to find CEC node\n");
cec_pdev = of_find_device_by_node(cec_np);
if (!cec_pdev) {
dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np);
of_node_put(cec_np);
return -EPROBE_DEFER;
}
of_node_put(cec_np);
ret = devm_add_action_or_reset(dev, mtk_hdmi_put_device, &cec_pdev->dev);
if (ret)
return ret;
/*
* The mediatek,syscon-hdmi property contains a phandle link to the
* MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
* registers it contains.
*/
hdmi->sys_regmap = syscon_regmap_lookup_by_phandle_args(np, "mediatek,syscon-hdmi",
1, &hdmi->sys_offset);
if (IS_ERR(hdmi->sys_regmap))
return dev_err_probe(dev, PTR_ERR(hdmi->sys_regmap),
"Failed to get system configuration registers\n");
hdmi->cec_dev = &cec_pdev->dev;
return 0;
}
static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device *pdev,
const char * const *clk_names, size_t num_clocks)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *remote, *i2c_np;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks);
if (ret)
return dev_err_probe(dev, ret, "Failed to get clocks\n");
hdmi->irq = platform_get_irq(pdev, 0);
if (!hdmi->irq)
return hdmi->irq;
hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs))
return PTR_ERR(hdmi->regs);
remote = of_graph_get_remote_node(np, 1, 0);
if (!remote)
return -EINVAL;
if (!of_device_is_compatible(remote, "hdmi-connector")) {
hdmi->next_bridge = of_drm_find_bridge(remote);
if (!hdmi->next_bridge) {
dev_err(dev, "Waiting for external bridge\n");
of_node_put(remote);
return -EPROBE_DEFER;
}
}
i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
of_node_put(remote);
if (!i2c_np)
return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
of_node_put(i2c_np);
if (!hdmi->ddc_adpt)
return dev_err_probe(dev, -EPROBE_DEFER, "Failed to get ddc i2c adapter by node\n");
ret = devm_add_action_or_reset(dev, mtk_hdmi_put_device, &hdmi->ddc_adpt->dev);
if (ret)
return ret;
ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
if (ret == -EOPNOTSUPP)
dev_info(dev, "CEC support unavailable: node not found\n");
else if (ret)
return ret;
return 0;
}
static void mtk_hdmi_unregister_audio_driver(void *data)
{
platform_device_unregister(data);
}
static int mtk_hdmi_register_audio_driver(struct device *dev)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
struct hdmi_audio_param *aud_param = &hdmi->aud_param;
struct hdmi_codec_pdata codec_data = {
.ops = hdmi->conf->ver_conf->codec_ops,
.max_i2s_channels = 2,
.i2s = 1,
.data = hdmi,
.no_capture_mute = 1,
};
int ret;
aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
hdmi->audio_pdev = platform_device_register_data(dev,
HDMI_CODEC_DRV_NAME,
PLATFORM_DEVID_AUTO,
&codec_data,
sizeof(codec_data));
if (IS_ERR(hdmi->audio_pdev))
return PTR_ERR(hdmi->audio_pdev);
ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
hdmi->audio_pdev);
if (ret)
return ret;
return 0;
}
struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
{
const struct mtk_hdmi_ver_conf *ver_conf;
const struct mtk_hdmi_conf *hdmi_conf;
struct device *dev = &pdev->dev;
struct mtk_hdmi *hdmi;
int ret;
hdmi_conf = of_device_get_match_data(dev);
if (!hdmi_conf)
return ERR_PTR(-ENODEV);
ver_conf = hdmi_conf->ver_conf;
hdmi = devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge,
ver_conf->bridge_funcs);
if (IS_ERR(hdmi))
return hdmi;
hdmi->dev = dev;
hdmi->conf = hdmi_conf;
hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
if (!hdmi->clk)
return ERR_PTR(-ENOMEM);
ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
ver_conf->num_clocks);
if (ret)
return ERR_PTR(ret);
hdmi->phy = devm_phy_get(dev, "hdmi");
if (IS_ERR(hdmi->phy))
return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n");
mutex_init(&hdmi->update_plugged_status_lock);
platform_set_drvdata(pdev, hdmi);
ret = mtk_hdmi_register_audio_driver(dev);
if (ret)
return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n");
hdmi->bridge.of_node = pdev->dev.of_node;
hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
| DRM_BRIDGE_OP_HPD;
if (ver_conf->bridge_funcs->hdmi_write_infoframe &&
ver_conf->bridge_funcs->hdmi_clear_infoframe)
hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI;
hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
hdmi->bridge.ddc = hdmi->ddc_adpt;
hdmi->bridge.vendor = "MediaTek";
hdmi->bridge.product = "On-Chip HDMI";
hdmi->bridge.interlace_allowed = ver_conf->interlace_allowed;
ret = devm_drm_bridge_add(dev, &hdmi->bridge);
if (ret)
return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n");
return hdmi;
}
EXPORT_SYMBOL_NS_GPL(mtk_hdmi_common_probe, "DRM_MTK_HDMI");
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
MODULE_DESCRIPTION("MediaTek HDMI Common Library");
MODULE_LICENSE("GPL");

198
drivers/gpu/drm/mediatek/mtk_hdmi_common.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
* Copyright (c) 2024 Collabora Ltd.
*/
#ifndef _MTK_HDMI_COMMON_H
#define _MTK_HDMI_COMMON_H
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_print.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/hdmi.h>
#include <linux/i2c.h>
#include <linux/mfd/syscon.h>
#include <linux/mutex.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <sound/hdmi-codec.h>
enum hdmi_aud_input_type {
HDMI_AUD_INPUT_I2S = 0,
HDMI_AUD_INPUT_SPDIF,
};
enum hdmi_aud_i2s_fmt {
HDMI_I2S_MODE_RJT_24BIT = 0,
HDMI_I2S_MODE_RJT_16BIT,
HDMI_I2S_MODE_LJT_24BIT,
HDMI_I2S_MODE_LJT_16BIT,
HDMI_I2S_MODE_I2S_24BIT,
HDMI_I2S_MODE_I2S_16BIT
};
enum hdmi_aud_mclk {
HDMI_AUD_MCLK_128FS,
HDMI_AUD_MCLK_192FS,
HDMI_AUD_MCLK_256FS,
HDMI_AUD_MCLK_384FS,
HDMI_AUD_MCLK_512FS,
HDMI_AUD_MCLK_768FS,
HDMI_AUD_MCLK_1152FS,
};
enum hdmi_aud_channel_type {
HDMI_AUD_CHAN_TYPE_1_0 = 0,
HDMI_AUD_CHAN_TYPE_1_1,
HDMI_AUD_CHAN_TYPE_2_0,
HDMI_AUD_CHAN_TYPE_2_1,
HDMI_AUD_CHAN_TYPE_3_0,
HDMI_AUD_CHAN_TYPE_3_1,
HDMI_AUD_CHAN_TYPE_4_0,
HDMI_AUD_CHAN_TYPE_4_1,
HDMI_AUD_CHAN_TYPE_5_0,
HDMI_AUD_CHAN_TYPE_5_1,
HDMI_AUD_CHAN_TYPE_6_0,
HDMI_AUD_CHAN_TYPE_6_1,
HDMI_AUD_CHAN_TYPE_7_0,
HDMI_AUD_CHAN_TYPE_7_1,
HDMI_AUD_CHAN_TYPE_3_0_LRS,
HDMI_AUD_CHAN_TYPE_3_1_LRS,
HDMI_AUD_CHAN_TYPE_4_0_CLRS,
HDMI_AUD_CHAN_TYPE_4_1_CLRS,
HDMI_AUD_CHAN_TYPE_6_1_CS,
HDMI_AUD_CHAN_TYPE_6_1_CH,
HDMI_AUD_CHAN_TYPE_6_1_OH,
HDMI_AUD_CHAN_TYPE_6_1_CHR,
HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
HDMI_AUD_CHAN_TYPE_6_0_CS,
HDMI_AUD_CHAN_TYPE_6_0_CH,
HDMI_AUD_CHAN_TYPE_6_0_OH,
HDMI_AUD_CHAN_TYPE_6_0_CHR,
HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
};
enum hdmi_aud_channel_swap_type {
HDMI_AUD_SWAP_LR,
HDMI_AUD_SWAP_LFE_CC,
HDMI_AUD_SWAP_LSRS,
HDMI_AUD_SWAP_RLS_RRS,
HDMI_AUD_SWAP_LR_STATUS,
};
struct hdmi_audio_param {
enum hdmi_audio_coding_type aud_codec;
enum hdmi_audio_sample_size aud_sample_size;
enum hdmi_aud_input_type aud_input_type;
enum hdmi_aud_i2s_fmt aud_i2s_fmt;
enum hdmi_aud_mclk aud_mclk;
enum hdmi_aud_channel_type aud_input_chan_type;
struct hdmi_codec_params codec_params;
};
enum hdmi_hpd_state {
HDMI_PLUG_OUT = 0,
HDMI_PLUG_IN_AND_SINK_POWER_ON,
HDMI_PLUG_IN_ONLY,
};
struct mtk_hdmi_ver_conf {
const struct drm_bridge_funcs *bridge_funcs;
const struct hdmi_codec_ops *codec_ops;
const char * const *mtk_hdmi_clock_names;
int num_clocks;
bool interlace_allowed;
};
struct mtk_hdmi_conf {
const struct mtk_hdmi_ver_conf *ver_conf;
bool tz_disabled;
bool cea_modes_only;
unsigned long max_mode_clock;
u32 reg_hdmi_tx_cfg;
};
struct mtk_hdmi {
struct drm_bridge bridge;
struct drm_bridge *next_bridge;
struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
struct device *dev;
const struct mtk_hdmi_conf *conf;
struct phy *phy;
struct device *cec_dev;
struct i2c_adapter *ddc_adpt;
struct clk **clk;
struct drm_display_mode mode;
bool dvi_mode;
struct regmap *sys_regmap;
unsigned int sys_offset;
struct regmap *regs;
struct platform_device *audio_pdev;
struct hdmi_audio_param aud_param;
bool audio_enable;
bool powered;
bool enabled;
unsigned int irq;
enum hdmi_hpd_state hpd;
hdmi_codec_plugged_cb plugged_cb;
struct device *codec_dev;
struct mutex update_plugged_status_lock;
};
static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
{
return container_of(b, struct mtk_hdmi, bridge);
}
int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);
void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
struct device *codec_dev);
int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt *daifmt,
struct hdmi_codec_params *params);
void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
unsigned int *n, unsigned int *cts);
bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode);
struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev);
#endif /* _MTK_HDMI_COMMON_H */

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drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* MediaTek HDMI v2 Display Data Channel Driver
*
* Copyright (c) 2021 MediaTek Inc.
* Copyright (c) 2021 BayLibre, SAS
* Copyright (c) 2024 Collabora Ltd.
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <drm/drm_edid.h>
#include "mtk_hdmi_common.h"
#include "mtk_hdmi_regs_v2.h"
#define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
#define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
#define SI2C_ADDR_READ 0xf4
#define SCDC_I2C_SLAVE_ADDRESS 0x54
struct mtk_hdmi_ddc {
struct device *dev;
struct regmap *regs;
struct clk *clk;
struct i2c_adapter adap;
};
static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
{
u32 val;
regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
if (val & DDC_I2C_BUS_LOW) {
regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
usleep_range(250, 300);
}
if (val & DDC_I2C_NO_ACK) {
u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
}
if (val & DDC_I2C_NO_ACK)
return -EIO;
return 0;
}
static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id,
u16 offset_id, u8 *wr_data)
{
u32 val;
int ret;
/* If down, rise bus for write operation */
mtk_ddc_check_and_rise_low_bus(ddc);
regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
if (wr_data) {
regmap_write(ddc->regs, SI2C_CTRL,
FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
FIELD_PREP(SI2C_WDATA, *wr_data) |
SI2C_WR);
}
regmap_write(ddc->regs, DDC_CTRL,
FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data == NULL ? 0 : 1) |
FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
FIELD_PREP(DDC_CTRL_ADDR, addr_id));
usleep_range(1000, 1250);
ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
!(val & DDC_I2C_IN_PROG), 500, 1000);
if (ret) {
dev_err(ddc->dev, "DDC I2C write timeout\n");
return ret;
}
/* The I2C bus might be down after WR operation: rise it again */
ret = mtk_ddc_check_and_rise_low_bus(ddc);
if (ret) {
dev_err(ddc->dev, "Error during write operation: No ACK\n");
return ret;
}
return 0;
}
static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,
u8 addr, u8 *puc_value, u16 data_cnt)
{
u16 dly_cnt, i, uc_idx;
u32 rem, temp_length, uc_read_count, val;
u64 loop_counter;
int ret;
mtk_ddc_check_and_rise_low_bus(ddc);
regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
if (data_cnt >= 16) {
temp_length = 16;
loop_counter = data_cnt;
rem = do_div(loop_counter, temp_length);
if (rem)
loop_counter++;
} else {
temp_length = data_cnt;
loop_counter = 1;
}
if (uc_dev >= DDC_ADDR)
dly_cnt = DDC2_DLY_CNT_EDID;
else
dly_cnt = DDC2_DLY_CNT;
regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
for (i = 0; i < loop_counter; i++) {
rem = data_cnt % 16;
if (i > 0 && i == (loop_counter - 1) && rem)
temp_length = rem;
/* 0x51 - 0x53: Flow control */
if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
regmap_write(ddc->regs, DDC_CTRL,
FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
} else {
u16 offset;
if (addr != 0x43)
offset = i * 16;
else
offset = 0;
regmap_write(ddc->regs, DDC_CTRL,
FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
}
usleep_range(5000, 5500);
ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
!(val & DDC_I2C_IN_PROG), 1000,
500 * (temp_length + 5));
if (ret) {
dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
return ret;
}
ret = mtk_ddc_check_and_rise_low_bus(ddc);
if (ret) {
dev_err(ddc->dev, "Error during read operation: No ACK\n");
return ret;
}
for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
unsigned int read_idx = i * 16 + uc_idx;
regmap_write(ddc->regs, SI2C_CTRL,
FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
SI2C_RD);
regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
regmap_write(ddc->regs, SI2C_CTRL,
FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
SI2C_CONFIRM_READ);
/*
* If HDMI IP gets reset during EDID read, DDC read
* operation will fail and its delay counter will be
* reset to 400.
*/
regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
return 0;
uc_read_count = read_idx + 1;
}
}
if (uc_read_count > U8_MAX)
dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
return uc_read_count;
}
static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
u8 data_addr, u16 data_cnt, u8 *pr_data)
{
int read_data_cnt;
u16 req_data_cnt;
if (!data_cnt) {
dev_err(ddc->dev, "Invalid DDCM read request\n");
return -EINVAL;
}
req_data_cnt = U8_MAX - data_addr + 1;
if (req_data_cnt > data_cnt)
req_data_cnt = data_cnt;
regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);
if (read_data_cnt < 0)
return read_data_cnt;
else if (read_data_cnt != req_data_cnt)
return -EINVAL;
return 0;
}
static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
u8 data_addr, u16 data_cnt, u8 *pr_data)
{
int i, ret;
regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
/*
* In case there is no payload data, just do a single write for the
* address only
*/
if (data_cnt == 0)
return mtk_ddc_wr_one(ddc, b_dev, data_addr, NULL);
i = 0;
do {
ret = mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data + i);
if (ret)
return ret;
} while (++i < data_cnt);
return 0;
}
static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
{
struct mtk_hdmi_ddc *ddc;
u8 offset = 0;
int i, ret;
ddc = adapter->algo_data;
for (i = 0; i < num; i++) {
struct i2c_msg *msg = &msgs[i];
if (!msg->buf) {
dev_err(ddc->dev, "No message buffer\n");
return -EINVAL;
}
if (msg->flags & I2C_M_RD) {
/*
* The underlying DDC hardware always issues a write request
* that assigns the read offset as part of the read operation,
* therefore, use the `offset` value assigned in the previous
* write request from drm_edid
*/
ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
msg->len, &msg->buf[0]);
if (ret)
return ret;
} else {
/*
* The HW needs the data offset, found in buf[0], in the
* DDC_CTRL register, and each byte of data, starting at
* buf[1], goes in the SI2C_WDATA register.
*/
ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
msg->len - 1, &msg->buf[1]);
if (ret)
return ret;
/*
* Store the offset value requested by drm_edid or by
* scdc to use in subsequent read requests.
*/
if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
msg->len == 1) {
offset = msg->buf[0];
}
}
}
return i;
}
static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
.master_xfer = mtk_hdmi_ddc_v2_xfer,
.functionality = mtk_hdmi_ddc_v2_func,
};
static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_hdmi_ddc *ddc;
int ret;
ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
if (!ddc)
return -ENOMEM;
ddc->dev = dev;
ddc->regs = device_node_to_regmap(dev->parent->of_node);
if (IS_ERR_OR_NULL(ddc->regs))
return dev_err_probe(dev,
IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
"Cannot get regmap\n");
ddc->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(ddc->clk))
return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
ddc->adap.owner = THIS_MODULE;
ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
ddc->adap.retries = 3;
ddc->adap.dev.of_node = dev->of_node;
ddc->adap.algo_data = ddc;
ddc->adap.dev.parent = &pdev->dev;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
pm_runtime_get_sync(dev);
ret = devm_i2c_add_adapter(dev, &ddc->adap);
if (ret < 0)
return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
platform_set_drvdata(pdev, ddc);
return 0;
}
static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
{ .compatible = "mediatek,mt8195-hdmi-ddc" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match);
struct platform_driver mtk_hdmi_ddc_v2_driver = {
.probe = mtk_hdmi_ddc_v2_probe,
.driver = {
.name = "mediatek-hdmi-ddc-v2",
.of_match_table = mtk_hdmi_ddc_v2_match,
},
};
module_platform_driver(mtk_hdmi_ddc_v2_driver);
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
MODULE_LICENSE("GPL");

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drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
* Copyright (c) 2021 BayLibre, SAS
* Copyright (c) 2024 Collabora Ltd.
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef _MTK_HDMI_REGS_H
#define _MTK_HDMI_REGS_H
/* HDMI_TOP Config */
#define TOP_CFG00 0x000
#define HDMI2_ON BIT(2)
#define HDMI_MODE_HDMI BIT(3)
#define SCR_ON BIT(4)
#define TMDS_PACK_MODE GENMASK(9, 8)
#define TMDS_PACK_MODE_8BPP 0
#define TMDS_PACK_MODE_10BPP 1
#define TMDS_PACK_MODE_12BPP 2
#define TMDS_PACK_MODE_16BPP 3
#define DEEPCOLOR_PKT_EN BIT(12)
#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16)
#define HDMI_ABIST_ENABLE BIT(31)
#define TOP_CFG01 0x004
#define CP_SET_MUTE_EN BIT(0)
#define CP_CLR_MUTE_EN BIT(1)
#define NULL_PKT_EN BIT(2)
#define NULL_PKT_VSYNC_HIGH_EN BIT(3)
/* HDMI_TOP Audio: Channel Mapping */
#define TOP_AUD_MAP 0x00c
#define SD0_MAP GENMASK(2, 0)
#define SD1_MAP GENMASK(6, 4)
#define SD2_MAP GENMASK(10, 8)
#define SD3_MAP GENMASK(14, 12)
#define SD4_MAP GENMASK(18, 16)
#define SD5_MAP GENMASK(22, 20)
#define SD6_MAP GENMASK(26, 24)
#define SD7_MAP GENMASK(30, 28)
/* Auxiliary Video Information (AVI) Infoframe */
#define TOP_AVI_HEADER 0x024
#define TOP_AVI_PKT00 0x028
#define TOP_AVI_PKT01 0x02C
#define TOP_AVI_PKT02 0x030
#define TOP_AVI_PKT03 0x034
#define TOP_AVI_PKT04 0x038
#define TOP_AVI_PKT05 0x03C
/* Audio Interface Infoframe */
#define TOP_AIF_HEADER 0x040
#define TOP_AIF_PKT00 0x044
#define TOP_AIF_PKT01 0x048
#define TOP_AIF_PKT02 0x04c
#define TOP_AIF_PKT03 0x050
/* Audio SPDIF Infoframe */
#define TOP_SPDIF_HEADER 0x054
#define TOP_SPDIF_PKT00 0x058
#define TOP_SPDIF_PKT01 0x05c
#define TOP_SPDIF_PKT02 0x060
#define TOP_SPDIF_PKT03 0x064
#define TOP_SPDIF_PKT04 0x068
#define TOP_SPDIF_PKT05 0x06c
#define TOP_SPDIF_PKT06 0x070
#define TOP_SPDIF_PKT07 0x074
/* Infoframes Configuration */
#define TOP_INFO_EN 0x01c
#define AVI_EN BIT(0)
#define SPD_EN BIT(1)
#define AUD_EN BIT(2)
#define CP_EN BIT(5)
#define VSIF_EN BIT(11)
#define AVI_EN_WR BIT(16)
#define SPD_EN_WR BIT(17)
#define AUD_EN_WR BIT(18)
#define CP_EN_WR BIT(21)
#define VSIF_EN_WR BIT(27)
#define TOP_INFO_RPT 0x020
#define AVI_RPT_EN BIT(0)
#define SPD_RPT_EN BIT(1)
#define AUD_RPT_EN BIT(2)
#define CP_RPT_EN BIT(5)
#define VSIF_RPT_EN BIT(11)
/* Vendor Specific Infoframe */
#define TOP_VSIF_HEADER 0x174
#define TOP_VSIF_PKT00 0x178
#define TOP_VSIF_PKT01 0x17c
#define TOP_VSIF_PKT02 0x180
#define TOP_VSIF_PKT03 0x184
#define TOP_VSIF_PKT04 0x188
#define TOP_VSIF_PKT05 0x18c
#define TOP_VSIF_PKT06 0x190
#define TOP_VSIF_PKT07 0x194
/* HDMI_TOP Misc */
#define TOP_MISC_CTLR 0x1a4
#define DEEP_COLOR_ADD BIT(4)
/* Hardware interrupts */
#define TOP_INT_STA00 0x1a8
#define TOP_INT_ENABLE00 0x1b0
#define HTPLG_R_INT BIT(0)
#define HTPLG_F_INT BIT(1)
#define PORD_R_INT BIT(2)
#define PORD_F_INT BIT(3)
#define HDMI_VSYNC_INT BIT(4)
#define HDMI_AUDIO_INT BIT(5)
#define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25)
#define TOP_INT_ENABLE01 0x1b4
#define TOP_INT_CLR00 0x1b8
#define TOP_INT_CLR01 0x1bc
/* Video Mute */
#define TOP_VMUTE_CFG1 0x1c8
#define REG_VMUTE_EN BIT(16)
/* HDMI Audio IP */
#define AIP_CTRL 0x400
#define CTS_SW_SEL BIT(0)
#define CTS_REQ_EN BIT(1)
#define MCLK_EN BIT(2)
#define NO_MCLK_CTSGEN_SEL BIT(3)
#define AUD_IN_EN BIT(8)
#define AUD_SEL_OWRT BIT(9)
#define SPDIF_EN BIT(13)
#define HBRA_ON BIT(14)
#define DSD_EN BIT(15)
#define I2S_EN GENMASK(19, 16)
#define HBR_FROM_SPDIF BIT(20)
#define CTS_CAL_N4 BIT(23)
#define SPDIF_INTERNAL_MODULE BIT(24)
#define AIP_N_VAL 0x404
#define AIP_CTS_SVAL 0x408
#define AIP_SPDIF_CTRL 0x40c
#define WR_1UI_LOCK BIT(0)
#define FS_OVERRIDE_WRITE BIT(1)
#define WR_2UI_LOCK BIT(2)
#define MAX_1UI_WRITE GENMASK(15, 8)
#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16)
#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20)
#define MAX_2UI_I2S_LFE_CC_SWAP BIT(1)
#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16)
#define AUD_ERR_THRESH GENMASK(29, 24)
#define I2S2DSD_EN BIT(30)
#define AIP_I2S_CTRL 0x410
#define FIFO0_MAP GENMASK(1, 0)
#define FIFO1_MAP GENMASK(3, 2)
#define FIFO2_MAP GENMASK(5, 4)
#define FIFO3_MAP GENMASK(7, 6)
#define I2S_1ST_BIT_NOSHIFT BIT(8)
#define I2S_DATA_DIR_LSB BIT(9)
#define JUSTIFY_RIGHT BIT(10)
#define WS_HIGH BIT(11)
#define VBIT_COMPRESSED BIT(12)
#define CBIT_ORDER_SAME BIT(13)
#define SCK_EDGE_RISE BIT(14)
#define AIP_I2S_CHST0 0x414
#define AIP_I2S_CHST1 0x418
#define AIP_TXCTRL 0x424
#define RST4AUDIO BIT(0)
#define RST4AUDIO_FIFO BIT(1)
#define RST4AUDIO_ACR BIT(2)
#define AUD_LAYOUT_1 BIT(4)
#define AUD_MUTE_FIFO_EN BIT(5)
#define AUD_PACKET_DROP BIT(6)
#define DSD_MUTE_EN BIT(7)
#define AIP_TPI_CTRL 0x428
#define TPI_AUDIO_LOOKUP_EN BIT(2)
/* Video downsampling configuration */
#define VID_DOWNSAMPLE_CONFIG 0x8d0
#define C444_C422_CONFIG_ENABLE BIT(0)
#define C422_C420_CONFIG_ENABLE BIT(4)
#define C422_C420_CONFIG_BYPASS BIT(5)
#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6)
#define VID_OUT_FORMAT 0x8fc
#define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10)
/* HDCP registers */
#define HDCP_TOP_CTRL 0xc00
#define HDCP2X_CTRL_0 0xc20
#define HDCP2X_EN BIT(0)
#define HDCP2X_ENCRYPT_EN BIT(7)
#define HDCP2X_HPD_OVR BIT(10)
#define HDCP2X_HPD_SW BIT(11)
#define HDCP2X_POL_CTRL 0xc54
#define HDCP2X_DIS_POLL_EN BIT(16)
#define HDCP1X_CTRL 0xcd0
#define HDCP1X_ENC_EN BIT(6)
/* HDMI DDC registers */
#define HPD_DDC_CTRL 0xc08
#define HPD_DDC_DELAY_CNT GENMASK(31, 16)
#define HPD_DDC_HPD_DBNC_EN BIT(2)
#define HPD_DDC_PORD_DBNC_EN BIT(3)
#define DDC_CTRL 0xc10
#define DDC_CTRL_ADDR GENMASK(7, 1)
#define DDC_CTRL_OFFSET GENMASK(15, 8)
#define DDC_CTRL_DIN_CNT GENMASK(25, 16)
#define DDC_CTRL_CMD GENMASK(31, 28)
#define SCDC_CTRL 0xc18
#define SCDC_DDC_SEGMENT GENMASK(15, 8)
#define HPD_DDC_STATUS 0xc60
#define HPD_STATE GENMASK(1, 0)
#define HPD_STATE_CONNECTED 2
#define HPD_PIN_STA BIT(4)
#define PORD_PIN_STA BIT(5)
#define DDC_I2C_IN_PROG BIT(13)
#define DDC_DATA_OUT GENMASK(23, 16)
#define SI2C_CTRL 0xcac
#define SI2C_WR BIT(0)
#define SI2C_RD BIT(1)
#define SI2C_CONFIRM_READ BIT(2)
#define SI2C_WDATA GENMASK(15, 8)
#define SI2C_ADDR GENMASK(23, 16)
/* HDCP DDC registers */
#define HDCP2X_DDCM_STATUS 0xc68
#define DDC_I2C_NO_ACK BIT(10)
#define DDC_I2C_BUS_LOW BIT(11)
/* HDMI TX registers */
#define HDMITX_CONFIG_MT8188 0xea0
#define HDMITX_CONFIG_MT8195 0x900
#define HDMI_YUV420_MODE BIT(10)
#define HDMITX_SW_HPD BIT(29)
#define HDMITX_SW_RSTB BIT(31)
/**
* enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands
* @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte
* @DDC_CMD_READ: Current address read with ACK on last byte
* @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte
* @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte
* @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte
* @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte
* @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte
* @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte
* @DDC_CMD_RSVD: Reserved for future use
* @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO
* @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL
* @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction
*/
enum mtk_hdmi_ddc_v2_cmds {
DDC_CMD_READ_NOACK = 0x0,
DDC_CMD_READ,
DDC_CMD_SEQ_READ_NOACK,
DDC_CMD_SEQ_READ,
DDC_CMD_ENH_READ_NOACK,
DDC_CMD_ENH_READ,
DDC_CMD_SEQ_WRITE_NOACK,
DDC_CMD_SEQ_WRITE = 0x07,
DDC_CMD_CLEAR_FIFO = 0x09,
DDC_CMD_CLOCK_SCL = 0x0a,
DDC_CMD_ABORT_XFER = 0x0f
};
#endif /* _MTK_HDMI_REGS_H */

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drivers/gpu/drm/mediatek/mtk_hdmi_v2.c Normal file
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