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arm64: dts: renesas: r9a09g087: Add ETHSS node

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Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/N2H
(R9A09G087) SoC. The ETHSS IP block is responsible for handling MII
pass-through or conversion to RMII/RGMII.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251028175458.1037397-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2025-10-28 17:54:55 +00:00
committed by Geert Uytterhoeven
parent fea7a8b7d7
commit 5d06389a05
1 changed files with 37 additions and 0 deletions
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37
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
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@@ -270,6 +270,43 @@
status = "disabled";
};
ethss: ethss@80110000 {
compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic";
reg = <0 0x80110000 0 0x10000>;
clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>,
<&cpg CPG_CORE R9A09G087_ETCLKB>,
<&cpg CPG_CORE R9A09G087_ETCLKD>,
<&cpg CPG_MOD 403>;
clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
resets = <&cpg 405>, <&cpg 406>;
reset-names = "rst", "crst";
power-domains = <&cpg>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
mii_conv0: mii-conv@0 {
reg = <0>;
status = "disabled";
};
mii_conv1: mii-conv@1 {
reg = <1>;
status = "disabled";
};
mii_conv2: mii-conv@2 {
reg = <2>;
status = "disabled";
};
mii_conv3: mii-conv@3 {
reg = <3>;
status = "disabled";
};
};
cpg: clock-controller@80280000 {
compatible = "renesas,r9a09g087-cpg-mssr";
reg = <0 0x80280000 0 0x1000>,