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dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI

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Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251021-dr1v90-basic-dt-v3-5-5478db4f664a@pigmoral.tech
This commit is contained in:
Junhui Liu
2025-10-21 17:41:40 +08:00
committed by Thomas Gleixner
parent b90ac5fe32
commit 579951da64
1 changed files with 11 additions and 6 deletions
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17
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
View File

@@ -4,18 +4,23 @@
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
title: ACLINT Machine-level Software Interrupt Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
items:
- enum:
- sophgo,sg2042-aclint-mswi
- sophgo,sg2044-aclint-mswi
- const: thead,c900-aclint-mswi
oneOf:
- items:
- enum:
- sophgo,sg2042-aclint-mswi
- sophgo,sg2044-aclint-mswi
- const: thead,c900-aclint-mswi
- items:
- enum:
- anlogic,dr1v90-aclint-mswi
- const: nuclei,ux900-aclint-mswi
reg:
maxItems: 1