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Merge tag 'stm32-dt-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt

Browse Source 
STM32 DT for v6.19, round 1

Highlights:
-----------

- MPU:
  - STM32MP13:
    - Add and enable the ARM SMC watchdog to use IWDG1 in the secure
      world.

  - STMP32MP15:
    - Phytec SOM: Fix STMPE811 touchscreen
    - LXA: drop unnecessary vusb_d/a-supply as already defined by
           "phy-supply" and "vdda1v8-supply".

  - STM32MP23:
    - Use the RIFSC as an access controler (firewall) as it is done
      for STM32MP25 and STM32MP23.

  - STM32MP25:
    - Add OSPI memory region name.
    - Add I/O synchronization properties to satisfy RGMII
      specification.

* tag 'stm32-dt-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  arm64: dts: st: set RIFSC as an access controller on stm32mp21x platforms
  ARM: dts: stm32: add the IWDG2 interrupt line in stm32mp131.dtsi
  ARM: dts: stm32: enable the ARM SMC watchdog node in stm32mp135f-dk
  ARM: dts: stm32: add the ARM SMC watchdog in stm32mp131.dtsi
  ARM: dts: stm32: add iwdg1 node in stm32mp131.dtsi
  arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsi
  arm64: dts: st: Add memory-region-names property for stm32mp257f-ev1
  ARM: dts: stm32: lxa: drop unnecessary vusb_d/a-supply
  ARM: dts: stm32: stm32mp157c-phycore: Fix STMPE811 touchscreen node properties

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-21 20:53:53 +01:00
parent bb4553b163 a6961e2ced
commit 5733ad88a5
8 changed files with 34 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/boot/dts/st/stm32mp131.dtsi
View File

@@ -29,6 +29,12 @@
interrupt-parent = <&intc>;
};
arm_wdt: watchdog {
compatible = "arm,smc-wdt";
arm,smc-id = <0xbc000000>;
status = "disabled";
};
firmware {
optee {
method = "smc";
@@ -1000,6 +1006,7 @@
iwdg2: watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
status = "disabled";
@@ -1657,6 +1664,16 @@
reg = <1>;
};
};
iwdg1: watchdog@5c003000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5c003000 0x400>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>;
clock-names = "pclk", "lsi";
access-controllers = <&etzpc 12>;
status = "disabled";
};
};
/*

5
arch/arm/boot/dts/st/stm32mp135f-dk.dts
View File

@@ -161,6 +161,11 @@
};
};
&arm_wdt {
timeout-sec = <32>;
status = "okay";
};
&crc1 {
status = "okay";
};

3
arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi
View File

@@ -374,9 +374,6 @@ baseboard_eeprom: &sip_eeprom {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
vusb_d-supply = <&vdd_usb>;
vusb_a-supply = <&reg18>;
status = "okay";
};

8
arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi
View File

@@ -185,13 +185,13 @@
interrupt-parent = <&gpioi>;
vio-supply = <&v3v3>;
vcc-supply = <&v3v3>;
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
touchscreen {
compatible = "st,stmpe-ts";
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;

3
arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi
View File

@@ -493,9 +493,6 @@ baseboard_eeprom: &sip_eeprom {
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
vusb_d-supply = <&vdd_usb>;
vusb_a-supply = <&reg18>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 16 16 16 16 16>;

4
arch/arm64/boot/dts/st/stm32mp211.dtsi
View File

@@ -94,18 +94,20 @@
#size-cells = <2>;
rifsc: bus@42080000 {
compatible = "simple-bus";
compatible = "st,stm32mp21-rifsc", "simple-bus";
reg = <0x42080000 0x0 0x1000>;
ranges;
dma-ranges;
#address-cells = <1>;
#size-cells = <2>;
#access-controller-cells = <1>;
usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x0 0x400>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_flexgen_08>;
access-controllers = <&rifsc 32>;
status = "disabled";
};
};

4
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
View File

@@ -38,6 +38,7 @@
bias-disable;
drive-push-pull;
slew-rate = <3>;
st,io-sync = "data on both edges";
};
pins2 {
pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
@@ -53,6 +54,7 @@
<STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
st,io-sync = "data on both edges";
};
pins4 {
pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
@@ -142,6 +144,7 @@
bias-disable;
drive-push-pull;
slew-rate = <3>;
st,io-sync = "data on both edges";
};
pins2 {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */
@@ -164,6 +167,7 @@
<STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
st,io-sync = "data on both edges";
};
pins5 {
pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */

1
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
View File

@@ -266,6 +266,7 @@
&ommanager {
memory-region = <&mm_ospi1>;
memory-region-names = "ospi1";
pinctrl-0 = <&ospi_port1_clk_pins_a
&ospi_port1_io03_pins_a
&ospi_port1_cs0_pins_a>;