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arm64: dts: renesas: rzg3s-smarc: Enable SSI3

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Enable SSI3.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241210170953.2936724-24-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea
2024-12-10 19:09:52 +02:00
committed by Geert Uytterhoeven
parent c3de00ac31
commit 558a25c2ee
1 changed files with 25 additions and 0 deletions
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25
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
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@@ -69,6 +69,10 @@
};
};
&audio_clk2 {
clock-frequency = <12288000>;
};
&i2c0 {
status = "okay";
@@ -110,6 +114,11 @@
};
&pinctrl {
audio_clock_pins: audio-clock {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
key-1-gpio-hog {
gpio-hog;
gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
@@ -167,6 +176,13 @@
pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
};
};
ssi3_pins: ssi3 {
pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
<RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
<RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
<RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
};
};
&scif0 {
@@ -187,3 +203,12 @@
max-frequency = <125000000>;
status = "okay";
};
&ssi3 {
clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
<&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
<&versa3 2>, <&audio_clk2>;
pinctrl-names = "default";
pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
status = "okay";
};