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net: stmmac: s32: move PHY_INTF_SEL_x definitions out of the way
S32's PHY_INTF_SEL_x definitions conflict with those for the dwmac cores as they use a different bitmapping. Add a S32 prefix so that they are unique. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Link: https://patch.msgid.link/E1vFt4S-0000000ChoS-2Ahi@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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committed by
Jakub Kicinski
parent
dec568a36f
commit
553f23d195
@@ -24,10 +24,10 @@
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#define GMAC_INTF_RATE_125M 125000000 /* 125MHz */
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/* SoC PHY interface control register */
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#define PHY_INTF_SEL_MII 0x00
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#define PHY_INTF_SEL_SGMII 0x01
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#define PHY_INTF_SEL_RGMII 0x02
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#define PHY_INTF_SEL_RMII 0x08
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#define S32_PHY_INTF_SEL_MII 0x00
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#define S32_PHY_INTF_SEL_SGMII 0x01
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#define S32_PHY_INTF_SEL_RGMII 0x02
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#define S32_PHY_INTF_SEL_RMII 0x08
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struct s32_priv_data {
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void __iomem *ioaddr;
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@@ -40,7 +40,7 @@ struct s32_priv_data {
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static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
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{
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writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
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writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
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dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));
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