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drm/amd/display: Add support for sRGB EOTF in BLND block
Expose a 3rd 1D curve colorop, with support for DRM_COLOROP_1D_CURVE_SRGB_EOTF and program the BLND block to perform the sRGB transform when the colorop is not in bypass With this change the following IGT test passes: kms_colorop --run plane-XR30-XR30-srgb_eotf-srgb_inv_eotf-srgb_eotf The color pipeline now consists of the following colorops: 1. 1D curve colorop w/ sRGB EOTF support 2. 1D curve colorop w/ sRGB Inverse EOTF support 3. 1D curve colorop w/ sRGB EOTF support Signed-off-by: Alex Hung <alex.hung@amd.com> Co-developed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Simon Ser <contact@emersion.fr> Link: https://patch.msgid.link/20251115000237.3561250-31-alex.hung@amd.com
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@@ -1304,6 +1304,70 @@ __set_dm_plane_colorop_shaper(struct drm_plane_state *plane_state,
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return __set_colorop_in_shaper_1d_curve(dc_plane_state, colorop_state);
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}
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static int
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__set_colorop_1d_curve_blend_tf_lut(struct dc_plane_state *dc_plane_state,
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struct drm_colorop_state *colorop_state)
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{
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struct dc_transfer_func *tf = &dc_plane_state->blend_tf;
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struct drm_colorop *colorop = colorop_state->colorop;
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struct drm_device *drm = colorop->dev;
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const struct drm_color_lut *blend_lut = NULL;
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u32 blend_size = 0;
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if (colorop->type != DRM_COLOROP_1D_CURVE &&
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colorop_state->curve_1d_type != DRM_COLOROP_1D_CURVE_SRGB_EOTF)
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return -EINVAL;
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if (colorop_state->bypass) {
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tf->type = TF_TYPE_BYPASS;
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tf->tf = TRANSFER_FUNCTION_LINEAR;
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return 0;
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}
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drm_dbg(drm, "Blend colorop with ID: %d\n", colorop->base.id);
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if (colorop->type == DRM_COLOROP_1D_CURVE) {
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tf->type = TF_TYPE_DISTRIBUTED_POINTS;
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tf->tf = amdgpu_colorop_tf_to_dc_tf(colorop_state->curve_1d_type);
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tf->sdr_ref_white_level = SDR_WHITE_LEVEL_INIT_VALUE;
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return __set_input_tf(NULL, tf, blend_lut, blend_size);
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}
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return -EINVAL;
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}
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static int
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__set_dm_plane_colorop_blend(struct drm_plane_state *plane_state,
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struct dc_plane_state *dc_plane_state,
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struct drm_colorop *colorop)
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{
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struct drm_colorop *old_colorop;
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struct drm_colorop_state *colorop_state = NULL, *new_colorop_state;
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struct drm_atomic_state *state = plane_state->state;
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int i = 0;
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old_colorop = colorop;
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/* 3nd op: 1d curve - blend */
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for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) {
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if (new_colorop_state->colorop == old_colorop &&
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new_colorop_state->curve_1d_type == DRM_COLOROP_1D_CURVE_SRGB_EOTF) {
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colorop_state = new_colorop_state;
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break;
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}
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if (new_colorop_state->colorop == old_colorop) {
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colorop_state = new_colorop_state;
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break;
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}
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}
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if (!colorop_state)
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return -EINVAL;
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return __set_colorop_1d_curve_blend_tf_lut(dc_plane_state, colorop_state);
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}
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static int
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amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state,
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struct dc_plane_state *dc_plane_state)
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@@ -1381,6 +1445,17 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state,
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if (ret)
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return ret;
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/* 1D Curve - BLND TF */
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colorop = colorop->next;
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if (!colorop) {
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drm_dbg(dev, "no Blend TF colorop found\n");
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return -EINVAL;
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}
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ret = __set_dm_plane_colorop_blend(plane_state, dc_plane_state, colorop);
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if (ret)
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return ret;
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return 0;
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}
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@@ -37,6 +37,9 @@ const u64 amdgpu_dm_supported_degam_tfs =
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const u64 amdgpu_dm_supported_shaper_tfs =
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BIT(DRM_COLOROP_1D_CURVE_SRGB_INV_EOTF);
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const u64 amdgpu_dm_supported_blnd_tfs =
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BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF);
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#define MAX_COLOR_PIPELINE_OPS 10
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int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list)
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@@ -77,6 +80,21 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr
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drm_colorop_set_next_property(ops[i - 1], ops[i]);
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i++;
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/* 1D curve - BLND TF */
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ops[i] = kzalloc(sizeof(*ops[0]), GFP_KERNEL);
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if (!ops[i]) {
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ret = -ENOMEM;
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goto cleanup;
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}
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ret = drm_plane_colorop_curve_1d_init(dev, ops[i], plane, amdgpu_dm_supported_blnd_tfs);
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if (ret)
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goto cleanup;
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drm_colorop_set_next_property(ops[i - 1], ops[i]);
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return 0;
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cleanup:
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@@ -29,6 +29,7 @@
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extern const u64 amdgpu_dm_supported_degam_tfs;
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extern const u64 amdgpu_dm_supported_shaper_tfs;
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extern const u64 amdgpu_dm_supported_blnd_tfs;
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int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_prop_enum_list *list);
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