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drm/ttm: add pgprot handling for RISC-V

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The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.

Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Han Gao <rabenda.cn@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Link: https://lore.kernel.org/r/20251020053523.731353-1-uwu@icenowy.me
This commit is contained in:
Icenowy Zheng
2025-10-20 13:35:23 +08:00
committed by Christian König
parent a80c98b6f0
commit 4f9ffd2c80
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/ttm/ttm_module.c
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@@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
#endif /* CONFIG_UML */
#endif /* __i386__ || __x86_64__ */
#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
defined(__riscv)
if (caching == ttm_write_combined)
tmp = pgprot_writecombine(tmp);
else