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drm/i915/display: perform transient flush

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Perform manual transient cache flush prior to flip and at the end of
frontbuffer_flush. This is needed to ensure display engine doesn't see
garbage if the surface is L3:XD dirty.

Testcase: igt@xe-pat@display-vs-wb-transient
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-19-radhakrishna.sripada@intel.com
This commit is contained in:
Matthew Auld
2024-04-30 10:28:49 -07:00
committed by Radhakrishna Sripada
parent c01c6066e6
commit 4071ada7ae
5 changed files with 45 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/i915/display/intel_display.c
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@@ -109,6 +109,7 @@
#include "intel_sdvo.h"
#include "intel_snps_phy.h"
#include "intel_tc.h"
#include "intel_tdf.h"
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
@@ -7233,6 +7234,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_atomic_commit_fence_wait(state);
intel_td_flush(dev_priv);
drm_atomic_helper_wait_for_dependencies(&state->base);
drm_dp_mst_atomic_wait_for_dependencies(&state->base);
intel_atomic_global_state_wait_for_dependencies(state);

2
drivers/gpu/drm/i915/display/intel_frontbuffer.c
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@@ -65,6 +65,7 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
#include "intel_psr.h"
#include "intel_tdf.h"
/**
* frontbuffer_flush - flush frontbuffer
@@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin);
might_sleep();
intel_td_flush(i915);
intel_drrs_flush(i915, frontbuffer_bits);
intel_psr_flush(i915, frontbuffer_bits, origin);
intel_fbc_flush(i915, frontbuffer_bits, origin);

25
drivers/gpu/drm/i915/display/intel_tdf.h Normal file
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@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2024 Intel Corporation
*/
#ifndef __INTEL_TDF_H__
#define __INTEL_TDF_H__
/*
* TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can
* be enabled through various PAT index modes. Idea is to use this caching mode
* when for example rendering onto the display surface, with the promise that
* KMD will ensure transient cache entries are always flushed by the time we do
* the display flip, since display engine is never coherent with CPU/GPU caches.
*/
struct drm_i915_private;
#ifdef I915
static inline void intel_td_flush(struct drm_i915_private *i915) {}
#else
void intel_td_flush(struct drm_i915_private *i915);
#endif
#endif

3
drivers/gpu/drm/xe/Makefile
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@@ -204,7 +204,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/xe_dsb_buffer.o \
display/xe_fb_pin.o \
display/xe_hdcp_gsc.o \
display/xe_plane_initial.o
display/xe_plane_initial.o \
display/xe_tdf.o
# SOC code shared with i915
xe-$(CONFIG_DRM_XE_DISPLAY) += \

13
drivers/gpu/drm/xe/display/xe_tdf.c Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: MIT
/*
* Copyright © 2024 Intel Corporation
*/
#include "xe_device.h"
#include "intel_display_types.h"
#include "intel_tdf.h"
void intel_td_flush(struct drm_i915_private *i915)
{
xe_device_td_flush(i915);
}