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drm/xe/uapi: Add block diagram of a device

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In order to make proper use the uAPI, a prerequisite is to understand
some key concepts about the discrete GPU devices which are supported
by the Xe driver. For example, some structs defined in the uAPI are an
abstraction of a hardware component with a specific role.

This diagram helps to build a mental representation of a device how it
is seen by the Xe driver. As written in the documentation, it does not
intend to be a literal representation of an existing device. A lot
more information could be added but the intention for the overview is
to keep it simple, and go into detail as needed in other sections.

v2: Add GT1 inside Tile0 (José Roberto de Souza)

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Mateusz Naklicki <mateusz.naklicki@intel.com>
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Francois Dugast
2023-12-15 15:45:49 +00:00
committed by Rodrigo Vivi
parent 535881a8c5
commit 33c6fda687
1 changed files with 39 additions and 0 deletions
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39
include/uapi/drm/xe_drm.h
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@@ -23,6 +23,45 @@ extern "C" {
* 5. uEvents
*/
/**
* DOC: Xe Device Block Diagram
*
* The diagram below represents a high-level simplification of a discrete
* GPU supported by the Xe driver. It shows some device components which
* are necessary to understand this API, as well as how their relations
* to each other. This diagram does not represent real hardware::
*
* ┌──────────────────────────────────────────────────────────────────┐
* │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │
* │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │
* │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │
* │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │
* │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │
* │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │
* │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
* │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │
* │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
* │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
* │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │
* │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
* │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
* │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │
* │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
* │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
* │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │
* │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
* │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
* │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │
* │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
* │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │
* │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
* │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │
* │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │
* └─────────────────────────────Device0───────┬──────────────────────┘
* │
* ───────────────────────┴────────── PCI bus
*/
/**
* DOC: Xe uAPI Overview
*