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arm64: xilinx: Put ethernet phys to mdio node

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All zynqmp boards have been already described via mdio node that's why also
convert zc1751. With using mdio node there is an option to add reset
property for the whole mdio bus.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com
This commit is contained in:
Michal Simek
2023-09-18 14:41:15 +02:00
parent fb1580d51c
commit 2da2ac3c8d
5 changed files with 43 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View File

@@ -98,8 +98,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

16
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View File

@@ -91,12 +91,16 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};

8
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
View File

@@ -88,8 +88,12 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};
};

26
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
View File

@@ -116,17 +116,21 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
};
};
};

8
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
View File

@@ -77,8 +77,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};