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drm/xe/irq: Check fuse mask for media engines

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Just like the other engines, check xe_hw_engine_mask_per_class() for VCS
and VECS to account for architectural availability of those registers.
With that, all the possibly available media engines can have their
interrupts enabled.

Bspec: 54030
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-20-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Lucas De Marchi
2025-10-16 19:26:39 -07:00
parent 490fa7863b
commit 22b7117ec8
2 changed files with 17 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/xe/regs/xe_irq_regs.h
View File

@@ -65,7 +65,10 @@
#define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF)
#define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF)
#define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF)
#define VCS4_VCS5_INTR_MASK XE_REG(0x1900b0, XE_REG_OPTION_VF)
#define VCS6_VCS7_INTR_MASK XE_REG(0x1900b4, XE_REG_OPTION_VF)
#define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF)
#define VECS2_VECS3_INTR_MASK XE_REG(0x1900d4, XE_REG_OPTION_VF)
#define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4)
#define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF)
#define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF)

17
drivers/gpu/drm/xe/xe_irq.c
View File

@@ -205,6 +205,8 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
}
if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
u32 vcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_DECODE);
u32 vecs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE);
u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
/* Enable interrupts for each engine class */
@@ -215,12 +217,21 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
/* Unmask interrupts for each engine instance */
val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
if (vcs_fuse_mask & (BIT(0) | BIT(1)))
xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
if (vcs_fuse_mask & (BIT(2) | BIT(3)))
xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
if (vcs_fuse_mask & (BIT(4) | BIT(5)))
xe_mmio_write32(mmio, VCS4_VCS5_INTR_MASK, val);
if (vcs_fuse_mask & (BIT(6) | BIT(7)))
xe_mmio_write32(mmio, VCS6_VCS7_INTR_MASK, val);
val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
if (vecs_fuse_mask & (BIT(0) | BIT(1)))
xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
if (vecs_fuse_mask & (BIT(2) | BIT(3)))
xe_mmio_write32(mmio, VECS2_VECS3_INTR_MASK, val);
/*
* the heci2 interrupt is enabled via the same register as the