admin/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2025-12-07 20:06:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: renesas: r9a09g057: Add TSU nodes

Browse Source 
The Renesas RZ/V2H SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing:
- TSU0, which is located near the DRP-AI block
- TSU1, which is located near the CPU and DRP-AI block

Since TSU1 is physically closer the CPU and the highest temperature
spot, it is used for CPU throttling through a passive trip and cooling
map. TSU0 is configured only with a critical trip.

Add TSU nodes along with thermal zones and keep them enabled in the SoC
DTSI.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251020143107.13974-4-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Ovidiu Panait
2025-10-20 14:31:07 +00:00
committed by Geert Uytterhoeven
parent 8c95f813d7
commit 1f77aced8c
1 changed files with 75 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

75
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@@ -65,6 +65,7 @@
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -75,6 +76,7 @@
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -85,6 +87,7 @@
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -95,6 +98,7 @@
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
#cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -285,6 +289,32 @@
resets = <&cpg 0x30>;
};
tsu0: thermal@11000000 {
compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
reg = <0 0x11000000 0 0x1000>;
interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "adi", "adcmpi";
clocks = <&cpg CPG_MOD 0x109>;
resets = <&cpg 0xf7>;
power-domains = <&cpg>;
#thermal-sensor-cells = <0>;
renesas,tsu-trim = <&sys 0x320>;
};
tsu1: thermal@14002000 {
compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu";
reg = <0 0x14002000 0 0x1000>;
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "adi", "adcmpi";
clocks = <&cpg CPG_MOD 0x10a>;
resets = <&cpg 0xf8>;
power-domains = <&cpg>;
#thermal-sensor-cells = <0>;
renesas,tsu-trim = <&sys 0x330>;
};
xspi: spi@11030000 {
compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi";
reg = <0 0x11030000 0 0x10000>,
@@ -1312,6 +1342,51 @@
snps,blen = <16 8 4 0 0 0 0>;
};
thermal-zones {
sensor1_thermal: sensor1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&tsu0>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
sensor2_thermal: sensor2-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&tsu1>;
cooling-maps {
map0 {
trip = <&sensor2_target>;
cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
<&cpu2 0 3>, <&cpu3 0 3>;
contribution = <1024>;
};
};
trips {
sensor2_target: trip-point {
temperature = <95000>;
hysteresis = <1000>;
type = "passive";
};
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,