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Merge tag 'tegra-for-6.19-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

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ARM: tegra: Device tree changes for v6.19-rc1

Add more host1x devices on Tegra114 and Tegra124, as well as CSI for
Tegra20 and Tegra30. Support for the Xiaomi Mi Pad is also added.

* tag 'tegra-for-6.19-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Add device-tree for Xiaomi Mi Pad (A0101)
  ARM: tegra: add CSI nodes for Tegra20 and Tegra30
  ARM: tegra: Add missing HOST1X device nodes on Tegra124
  ARM: tegra: Add missing HOST1X device nodes on Tegra114

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-11-21 16:50:42 +01:00
parent 5d5b665e3e f224e936da
commit 17aaeb67e1
6 changed files with 2960 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/nvidia/Makefile
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@@ -11,7 +11,8 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-nyan-big.dtb \
tegra124-nyan-big-fhd.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
tegra124-venice2.dtb \
tegra124-xiaomi-mocha.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-asus-sl101.dtb \

64
arch/arm/boot/dts/nvidia/tegra114.dtsi
View File

@@ -48,6 +48,45 @@
ranges = <0x54000000 0x54000000 0x01000000>;
vi@54080000 {
compatible = "nvidia,tegra114-vi";
reg = <0x54080000 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
iommus = <&mc TEGRA_SWGROUP_VI>;
status = "disabled";
};
epp@540c0000 {
compatible = "nvidia,tegra114-epp";
reg = <0x540c0000 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_EPP>;
resets = <&tegra_car TEGRA114_CLK_EPP>;
reset-names = "epp";
iommus = <&mc TEGRA_SWGROUP_EPP>;
status = "disabled";
};
isp@54100000 {
compatible = "nvidia,tegra114-isp";
reg = <0x54100000 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_ISP>;
resets = <&tegra_car TEGRA114_CLK_ISP>;
reset-names = "isp";
iommus = <&mc TEGRA_SWGROUP_ISP>;
status = "disabled";
};
gr2d@54140000 {
compatible = "nvidia,tegra114-gr2d";
reg = <0x54140000 0x00040000>;
@@ -150,6 +189,31 @@
#address-cells = <1>;
#size-cells = <0>;
};
msenc@544c0000 {
compatible = "nvidia,tegra114-msenc";
reg = <0x544c0000 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_MSENC>;
resets = <&tegra_car TEGRA114_CLK_MSENC>;
reset-names = "mpe";
iommus = <&mc TEGRA_SWGROUP_MSENC>;
status = "disabled";
};
tsec@54500000 {
compatible = "nvidia,tegra114-tsec";
reg = <0x54500000 0x00040000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
resets = <&tegra_car TEGRA114_CLK_TSEC>;
iommus = <&mc TEGRA_SWGROUP_TSEC>;
status = "disabled";
};
};
gic: interrupt-controller@50041000 {

2790
arch/arm/boot/dts/nvidia/tegra124-xiaomi-mocha.dts Normal file
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File diff suppressed because it is too large Load Diff

64
arch/arm/boot/dts/nvidia/tegra124.dtsi
View File

@@ -103,6 +103,45 @@
ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
vi@54080000 {
compatible = "nvidia,tegra124-vi";
reg = <0x0 0x54080000 0x0 0x00040000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_VI>;
resets = <&tegra_car 20>;
reset-names = "vi";
iommus = <&mc TEGRA_SWGROUP_VI>;
status = "disabled";
};
isp@54600000 {
compatible = "nvidia,tegra124-isp";
reg = <0x0 0x54600000 0x0 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_ISP>;
resets = <&tegra_car TEGRA124_CLK_ISP>;
reset-names = "isp";
iommus = <&mc TEGRA_SWGROUP_ISP2>;
status = "disabled";
};
isp@54680000 {
compatible = "nvidia,tegra124-isp";
reg = <0x0 0x54680000 0x0 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_ISPB>;
resets = <&tegra_car TEGRA124_CLK_ISPB>;
reset-names = "isp";
iommus = <&mc TEGRA_SWGROUP_ISP2B>;
status = "disabled";
};
dc@54200000 {
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
@@ -209,6 +248,31 @@
#size-cells = <0>;
};
msenc@544c0000 {
compatible = "nvidia,tegra124-msenc";
reg = <0x0 0x544c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_MSENC>;
resets = <&tegra_car TEGRA124_CLK_MSENC>;
reset-names = "mpe";
iommus = <&mc TEGRA_SWGROUP_MSENC>;
status = "disabled";
};
tsec@54500000 {
compatible = "nvidia,tegra124-tsec";
reg = <0x0 0x54500000 0x0 0x00040000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSEC>;
resets = <&tegra_car TEGRA124_CLK_TSEC>;
iommus = <&mc TEGRA_SWGROUP_TSEC>;
status = "disabled";
};
sor@54540000 {
compatible = "nvidia,tegra124-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;

19
arch/arm/boot/dts/nvidia/tegra20.dtsi
View File

@@ -64,7 +64,7 @@
vi@54080000 {
compatible = "nvidia,tegra20-vi";
reg = <0x54080000 0x00040000>;
reg = <0x54080000 0x00000800>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_VI>;
resets = <&tegra_car 20>;
@@ -72,6 +72,23 @@
power-domains = <&pd_venc>;
operating-points-v2 = <&vi_dvfs_opp_table>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54080000 0x4000>;
csi: csi@800 {
compatible = "nvidia,tegra20-csi";
reg = <0x800 0x200>;
clocks = <&tegra_car TEGRA20_CLK_CSI>;
power-domains = <&pd_venc>;
#nvidia,mipi-calibrate-cells = <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
epp@540c0000 {

24
arch/arm/boot/dts/nvidia/tegra30.dtsi
View File

@@ -150,8 +150,8 @@
};
vi@54080000 {
compatible = "nvidia,tegra30-vi";
reg = <0x54080000 0x00040000>;
compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi";
reg = <0x54080000 0x00000800>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_VI>;
resets = <&tegra_car 20>;
@@ -162,6 +162,26 @@
iommus = <&mc TEGRA_SWGROUP_VI>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54080000 0x4000>;
csi: csi@800 {
compatible = "nvidia,tegra30-csi";
reg = <0x800 0x200>;
clocks = <&tegra_car TEGRA30_CLK_CSI>,
<&tegra_car TEGRA30_CLK_CSIA_PAD>,
<&tegra_car TEGRA30_CLK_CSIB_PAD>;
clock-names = "csi", "csia-pad", "csib-pad";
power-domains = <&pd_venc>;
#nvidia,mipi-calibrate-cells = <1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
epp@540c0000 {