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drm/amd/pm: enable more Pstates profile levels for SMU v13.0.5

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This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.

- profile_peak
- profile_min_sclk
- profile_standard

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tim Huang
2023-06-09 13:29:37 +08:00
committed by Alex Deucher
parent fdc95df9c2
commit 121f17ac42
2 changed files with 39 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
View File

@@ -978,6 +978,38 @@ force_level_out:
return ret;
}
static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum smu_clk_type clk_type,
uint32_t *min_clk,
uint32_t *max_clk)
{
int ret = 0;
uint32_t clk_limit = 0;
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
break;
case SMU_VCLK:
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
break;
case SMU_DCLK:
smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
break;
default:
ret = -EINVAL;
break;
}
*min_clk = *max_clk = clk_limit;
return ret;
}
static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
@@ -1011,10 +1043,14 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
/* Temporarily do nothing since the optimal clocks haven't been provided yet */
smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");
return -EOPNOTSUPP;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
return 0;

2
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h
View File

@@ -24,6 +24,6 @@
#define __SMU_V13_0_5_PPT_H__
extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);
#define SMU_13_0_5_UMD_PSTATE_GFXCLK 1100
#define SMU_13_0_5_UMD_PSTATE_GFXCLK 700
#endif