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riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1

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Enable SPI NOR node for SG2042_EVB_V1 device tree

According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-3-b5d9024fe1c8@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Zixian Zeng
2025-09-16 21:22:52 +08:00
committed by Inochi Amaoto
parent f49314cbbc
commit 11f4d84c9f
1 changed files with 24 additions and 0 deletions
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24
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
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@@ -250,6 +250,30 @@
status = "okay";
};
&spifmc0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&spifmc1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";