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Merge branch 'icc-sa8775p' into icc-next

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This enables QoS configuration for QNOC type device which can be found
on SA8775P platform. It enables QoS configuration for master ports with
predefined priority and urgency forwarding. This helps in prioritizing
the traffic originating from different interconnect masters at NOC.
The system may function normally without this feature. However, enabling
QoS helps optimize latency and bandwidth across subsystems like CPU, GPU,
and multimedia engines, which becomes important in high-throughput
scenarios. This is a feature aimed at performance enhancement to improve
system performance under concurrent workloads.

* icc-sa8775p
  dt-bindings: interconnect: add reg and clocks properties to enable QoS on sa8775p
  interconnect: qcom: sa8775p: enable QoS configuration

Link: https://lore.kernel.org/r/20251001073344.6599-1-odelu.kukatla@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
2025-10-31 03:07:20 +02:00
parent b4e8b0f2d1 3c046c3e04
commit 10ae71c96e
2 changed files with 489 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml
View File

@@ -33,18 +33,66 @@ properties:
- qcom,sa8775p-pcie-anoc
- qcom,sa8775p-system-noc
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 5
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sa8775p-aggre1-noc
then:
properties:
clocks:
items:
- description: aggre UFS PHY AXI clock
- description: aggre QUP PRIM AXI clock
- description: aggre USB2 PRIM AXI clock
- description: aggre USB3 PRIM AXI clock
- description: aggre USB3 SEC AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,sa8775p-aggre2-noc
then:
properties:
clocks:
items:
- description: aggre UFS CARD AXI clock
- description: RPMH CC IPA clock
unevaluatedProperties: false
examples:
- |
aggre1_noc: interconnect-aggre1-noc {
compatible = "qcom,sa8775p-aggre1-noc";
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
clk_virt: interconnect-clk-virt {
compatible = "qcom,sa8775p-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16c0000 {
compatible = "qcom,sa8775p-aggre1-noc";
reg = <0x016c0000 0x18080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
};

439
drivers/interconnect/qcom/sa8775p.c
View File

@@ -213,6 +213,13 @@ static struct qcom_icc_node qxm_qup3 = {
.name = "qxm_qup3",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x11000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -221,6 +228,13 @@ static struct qcom_icc_node xm_emac_0 = {
.name = "xm_emac_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -229,6 +243,13 @@ static struct qcom_icc_node xm_emac_1 = {
.name = "xm_emac_1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -237,6 +258,13 @@ static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -245,6 +273,13 @@ static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -253,6 +288,13 @@ static struct qcom_icc_node xm_usb2_2 = {
.name = "xm_usb2_2",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -261,6 +303,13 @@ static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -269,6 +318,13 @@ static struct qcom_icc_node xm_usb3_1 = {
.name = "xm_usb3_1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc },
};
@@ -277,6 +333,13 @@ static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -285,6 +348,13 @@ static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -293,6 +363,13 @@ static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -301,6 +378,13 @@ static struct qcom_icc_node qhm_qup2 = {
.name = "qhm_qup2",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -309,6 +393,13 @@ static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -317,6 +408,13 @@ static struct qcom_icc_node qxm_crypto_0 = {
.name = "qxm_crypto_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -325,6 +423,13 @@ static struct qcom_icc_node qxm_crypto_1 = {
.name = "qxm_crypto_1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x1a000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -333,6 +438,13 @@ static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x11000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -341,6 +453,13 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.name = "xm_qdss_etr_0",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -349,6 +468,13 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.name = "xm_qdss_etr_1",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x19000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -357,6 +483,13 @@ static struct qcom_icc_node xm_ufs_card = {
.name = "xm_ufs_card",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x1b000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc },
};
@@ -461,6 +594,13 @@ static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb4000 },
.prio_fwd_disable = 1,
.prio = 1,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -469,6 +609,13 @@ static struct qcom_icc_node alm_pcie_tcu = {
.name = "alm_pcie_tcu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb5000 },
.prio_fwd_disable = 1,
.prio = 3,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -477,6 +624,13 @@ static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb6000 },
.prio_fwd_disable = 1,
.prio = 6,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -494,6 +648,13 @@ static struct qcom_icc_node qnm_cmpnoc0 = {
.name = "qnm_cmpnoc0",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf3000, 0xf4000 },
.prio_fwd_disable = 1,
.prio = 0,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -502,6 +663,13 @@ static struct qcom_icc_node qnm_cmpnoc1 = {
.name = "qnm_cmpnoc1",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf5000, 0xf6000 },
.prio_fwd_disable = 1,
.prio = 0,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -527,6 +695,13 @@ static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xed000, 0xee000 },
.prio_fwd_disable = 1,
.prio = 0,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -535,6 +710,13 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xef000, 0xf0000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_llcc, &qns_pcie },
};
@@ -543,6 +725,13 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
.channels = 2,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 2,
.port_offsets = { 0xf1000, 0xf2000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
@@ -552,6 +741,13 @@ static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb8000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 2,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc },
};
@@ -560,6 +756,13 @@ static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb9000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_llcc },
};
@@ -568,6 +771,13 @@ static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xba000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 3,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gem_noc_cnoc, &qns_llcc,
&qns_pcie },
@@ -620,6 +830,13 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.name = "qnm_camnoc_hf",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
@@ -628,6 +845,13 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.name = "qnm_camnoc_icp",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
@@ -636,6 +860,13 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.name = "qnm_camnoc_sf",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a080 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
@@ -644,6 +875,13 @@ static struct qcom_icc_node qnm_mdp0_0 = {
.name = "qnm_mdp0_0",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa080 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
@@ -652,6 +890,13 @@ static struct qcom_icc_node qnm_mdp0_1 = {
.name = "qnm_mdp0_1",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa180 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
@@ -660,6 +905,13 @@ static struct qcom_icc_node qnm_mdp1_0 = {
.name = "qnm_mdp1_0",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa100 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
@@ -668,6 +920,13 @@ static struct qcom_icc_node qnm_mdp1_1 = {
.name = "qnm_mdp1_1",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xa200 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf },
};
@@ -692,6 +951,13 @@ static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a100 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
@@ -700,6 +966,13 @@ static struct qcom_icc_node qnm_video1 = {
.name = "qnm_video1",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a180 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
@@ -708,6 +981,13 @@ static struct qcom_icc_node qnm_video_cvp = {
.name = "qnm_video_cvp",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a200 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
@@ -716,6 +996,13 @@ static struct qcom_icc_node qnm_video_v_cpu = {
.name = "qnm_video_v_cpu",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x2a280 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf },
};
@@ -756,6 +1043,13 @@ static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
};
@@ -764,6 +1058,13 @@ static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
.channels = 1,
.buswidth = 32,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_mem_noc },
};
@@ -772,6 +1073,13 @@ static struct qcom_icc_node qhm_gic = {
.name = "qhm_gic",
.channels = 1,
.buswidth = 4,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
};
@@ -796,6 +1104,13 @@ static struct qcom_icc_node qnm_lpass_noc = {
.name = "qnm_lpass_noc",
.channels = 1,
.buswidth = 16,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio_fwd_disable = 0,
.prio = 0,
.urg_fwd = 1,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf },
};
@@ -812,6 +1127,13 @@ static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
};
@@ -820,6 +1142,13 @@ static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.channels = 1,
.buswidth = 8,
.qosbox = &(const struct qcom_icc_qosbox) {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio_fwd_disable = 1,
.prio = 2,
.urg_fwd = 0,
},
.num_links = 1,
.link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_gc },
};
@@ -1836,12 +2165,22 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = {
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
};
static const struct regmap_config sa8775p_aggre1_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x18080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_aggre1_noc = {
.config = &sa8775p_aggre1_noc_regmap_config,
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
.alloc_dyn_id = true,
.qos_requires_clocks = true,
};
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
@@ -1864,12 +2203,22 @@ static struct qcom_icc_node * const aggre2_noc_nodes[] = {
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
};
static const struct regmap_config sa8775p_aggre2_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1b080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_aggre2_noc = {
.config = &sa8775p_aggre2_noc_regmap_config,
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
.alloc_dyn_id = true,
.qos_requires_clocks = true,
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
@@ -1995,7 +2344,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = {
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static const struct regmap_config sa8775p_config_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x13080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_config_noc = {
.config = &sa8775p_config_noc_regmap_config,
.nodes = config_noc_nodes,
.num_nodes = ARRAY_SIZE(config_noc_nodes),
.bcms = config_noc_bcms,
@@ -2012,7 +2370,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = {
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
};
static const struct regmap_config sa8775p_dc_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_dc_noc = {
.config = &sa8775p_dc_noc_regmap_config,
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
@@ -2049,7 +2416,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = {
[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
};
static const struct regmap_config sa8775p_gem_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xf6080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_gem_noc = {
.config = &sa8775p_gem_noc_regmap_config,
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
@@ -2068,7 +2444,16 @@ static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
};
static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xe080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
.config = &sa8775p_gpdsp_anoc_regmap_config,
.nodes = gpdsp_anoc_nodes,
.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
.bcms = gpdsp_anoc_bcms,
@@ -2092,7 +2477,16 @@ static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
};
static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x17200,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
.config = &sa8775p_lpass_ag_noc_regmap_config,
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
@@ -2143,7 +2537,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = {
[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
};
static const struct regmap_config sa8775p_mmss_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x40000,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_mmss_noc = {
.config = &sa8775p_mmss_noc_regmap_config,
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
@@ -2164,7 +2567,16 @@ static struct qcom_icc_node * const nspa_noc_nodes[] = {
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
};
static const struct regmap_config sa8775p_nspa_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x16080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_nspa_noc = {
.config = &sa8775p_nspa_noc_regmap_config,
.nodes = nspa_noc_nodes,
.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
.bcms = nspa_noc_bcms,
@@ -2177,6 +2589,14 @@ static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
&bcm_nsb1,
};
static const struct regmap_config sa8775p_nspb_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x16080,
.fast_io = true,
};
static struct qcom_icc_node * const nspb_noc_nodes[] = {
[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
[MASTER_CDSP_PROC_B] = &qxm_nspb,
@@ -2186,6 +2606,7 @@ static struct qcom_icc_node * const nspb_noc_nodes[] = {
};
static const struct qcom_icc_desc sa8775p_nspb_noc = {
.config = &sa8775p_nspb_noc_regmap_config,
.nodes = nspb_noc_nodes,
.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
.bcms = nspb_noc_bcms,
@@ -2203,7 +2624,16 @@ static struct qcom_icc_node * const pcie_anoc_nodes[] = {
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
};
static const struct regmap_config sa8775p_pcie_anoc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0xc080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_pcie_anoc = {
.config = &sa8775p_pcie_anoc_regmap_config,
.nodes = pcie_anoc_nodes,
.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
.bcms = pcie_anoc_bcms,
@@ -2232,7 +2662,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = {
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
};
static const struct regmap_config sa8775p_system_noc_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x15080,
.fast_io = true,
};
static const struct qcom_icc_desc sa8775p_system_noc = {
.config = &sa8775p_system_noc_regmap_config,
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,