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drm/msm/a8xx: Add support for Adreno 840 GPU

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Adreno 840 present in Kaanapali SoC is the second generation GPU in
A8x family. It comes in 2 variants with either 2 or 3 Slices. This is
in addition to the SKUs supported based on the GPU FMAX.

Add the necessary register configurations to the catalog and enable
support for it.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689022/
Message-ID: <20251118-kaana-gpu-support-v4-16-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen
2025-11-18 14:20:43 +05:30
committed by Rob Clark
parent 16201a1ee2
commit 0700b9f682
5 changed files with 174 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

159
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
View File

@@ -1628,6 +1628,164 @@ static const struct adreno_info a7xx_gpus[] = {
};
DECLARE_ADRENO_GPULIST(a7xx);
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
/* Disable Dead Draw Merge scheme on RB-HLSQ */
{ REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
/* Partially enable perf clear, Disable DINT to c/z be data forwarding */
{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
/* Disable mode_switch optimization in UMAS */
{ REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) },
/* Disable LPAC large-LM mode */
{ REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) },
/* Disable PS out of order retire */
{ REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) },
{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
/* Disable SP2TP info attribute */
{ REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) },
{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) },
/* Ignore HLSQ shared constant feedback from SP */
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) },
/* Disable CS dead batch merge */
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) },
{ REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) },
{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
/* BIT(26): Disable final clamp for bicubic filtering */
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
{ },
};
static const u32 a840_protect_regs[] = {
A6XX_PROTECT_RDONLY(0x00008, 0x039b),
A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
A6XX_PROTECT_NORDWR(0x00440, 0x001f),
A6XX_PROTECT_RDONLY(0x00580, 0x005f),
A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
A6XX_PROTECT_RDONLY(0x00759, 0x001b),
A6XX_PROTECT_NORDWR(0x00775, 0x000a),
A6XX_PROTECT_RDONLY(0x00789, 0x0000),
A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
A6XX_PROTECT_NORDWR(0x00800, 0x0029),
A6XX_PROTECT_NORDWR(0x00837, 0x00af),
A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
A6XX_PROTECT_NORDWR(0x18400, 0x003f),
A6XX_PROTECT_RDONLY(0x18440, 0x013f),
A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
A6XX_PROTECT_NORDWR(0x27800, 0x007f),
A6XX_PROTECT_RDONLY(0x27880, 0x0385),
A6XX_PROTECT_NORDWR(0x27882, 0x0009),
A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
};
DECLARE_ADRENO_PROTECT(a840_protect, 15);
static const struct adreno_info a8xx_gpus[] = {
{
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
.family = ADRENO_8XX_GEN2,
.fw = {
[ADRENO_FW_SQE] = "gen80200_sqe.fw",
[ADRENO_FW_GMU] = "gen80200_gmu.bin",
[ADRENO_FW_AQE] = "gen80200_aqe.fw",
},
.gmem = 18 * SZ_1M,
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
ADRENO_QUIRK_HAS_HW_APRIV,
.funcs = &a8xx_gpu_funcs,
.a6xx = &(const struct a6xx_info) {
.protect = &a840_protect,
.nonctxt_reglist = a840_nonctxt_regs,
.max_slices = 3,
.gmu_chipid = 0x8020100,
.bcms = (const struct a6xx_bcm[]) {
{ .name = "SH0", .buswidth = 16 },
{ .name = "MC0", .buswidth = 4 },
{
.name = "ACV",
.fixed = true,
.perfmode = BIT(2),
.perfmode_bw = 10687500,
},
{ /* sentinel */ },
},
},
.preempt_record_size = 19708 * SZ_1K,
}
};
DECLARE_ADRENO_GPULIST(a8xx);
static inline __always_unused void __build_asserts(void)
{
BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
@@ -1635,4 +1793,5 @@ static inline __always_unused void __build_asserts(void)
BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
BUILD_BUG_ON(a840_protect.count > a840_protect.count_max);
}

8
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View File

@@ -601,16 +601,22 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
{
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
u32 bitmask = BIT(16);
int ret;
u32 val;
if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status))
return;
if (adreno_is_a840(adreno_gpu))
bitmask = BIT(30);
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
val, val & (1 << 16), 100, 10000);
val, val & bitmask, 100, 10000);
if (ret)
DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");

1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@@ -228,6 +228,7 @@ struct a7xx_cp_smmu_info {
extern const struct adreno_gpu_funcs a6xx_gpu_funcs;
extern const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs;
extern const struct adreno_gpu_funcs a7xx_gpu_funcs;
extern const struct adreno_gpu_funcs a8xx_gpu_funcs;
static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
{

2
drivers/gpu/drm/msm/adreno/adreno_device.c
View File

@@ -34,6 +34,7 @@ extern const struct adreno_gpulist a4xx_gpulist;
extern const struct adreno_gpulist a5xx_gpulist;
extern const struct adreno_gpulist a6xx_gpulist;
extern const struct adreno_gpulist a7xx_gpulist;
extern const struct adreno_gpulist a8xx_gpulist;
static const struct adreno_gpulist *gpulists[] = {
&a2xx_gpulist,
@@ -42,6 +43,7 @@ static const struct adreno_gpulist *gpulists[] = {
&a5xx_gpulist,
&a6xx_gpulist,
&a7xx_gpulist,
&a8xx_gpulist,
};
static const struct adreno_info *adreno_info(uint32_t chip_id)

5
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@@ -580,6 +580,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
return gpu->info->family >= ADRENO_8XX_GEN1;
}
static inline int adreno_is_a840(struct adreno_gpu *gpu)
{
return gpu->info->chip_ids[0] == 0x44050a01;
}
/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
#define ADRENO_VM_START 0x100000000ULL
u64 adreno_private_vm_size(struct msm_gpu *gpu);