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Renesas created different watchdog IPs but they are all handled in the same binding documentation. This leads to a lot of conditional handling which makes it unnecessarily hard to add new items. Factor out the RZ/V2H(P) watchdog to make handling easier. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
100 lines
2.0 KiB
YAML
100 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/renesas,r9a09g057-wdt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Watchdog Timer (WDT) Controller
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,r9a09g047-wdt # RZ/G3E
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- renesas,r9a09g056-wdt # RZ/V2N
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- const: renesas,r9a09g057-wdt # RZ/V2H(P)
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- items:
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- const: renesas,r9a09g087-wdt # RZ/N2H
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- const: renesas,r9a09g077-wdt # RZ/T2H
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- enum:
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- renesas,r9a09g057-wdt # RZ/V2H(P)
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- renesas,r9a09g077-wdt # RZ/T2H
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reg:
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minItems: 1
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maxItems: 2
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clocks:
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minItems: 1
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items:
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- description: Register access clock
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- description: Main clock
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clock-names:
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minItems: 1
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items:
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- const: pclk
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- const: oscclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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timeout-sec: true
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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allOf:
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- $ref: watchdog.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g057-wdt
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then:
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properties:
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reg:
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maxItems: 1
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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reg:
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minItems: 2
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resets: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
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watchdog@11c00400 {
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compatible = "renesas,r9a09g057-wdt";
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reg = <0x11c00400 0x400>;
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clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
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clock-names = "pclk", "oscclk";
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resets = <&cpg 0x75>;
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power-domains = <&cpg>;
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};
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