Maxime Ripard fa4d0ca104 clk: sunxi: Add PLL3 clock ...

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

2016-04-22 00:29:23 +02:00

..

bindings

clk: sunxi: Add PLL3 clock

2016-04-22 00:29:23 +02:00

00-INDEX

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booting-without-of.txt

sh: add device tree support and generic board using device tree

2016-03-17 19:46:11 +00:00

changesets.txt

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dynamic-resolution-notes.txt

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of_unittest.txt

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overlay-notes.txt

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todo.txt

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usage-model.txt

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