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384c57ec72
Each xHCI roothub port has a Port Link Info (PORTLI) register that is used by USB3 and eUSB2V2 ports. USB3 ports show link error count, rx lane count, and tx lane count. eUSB2V2 ports show Rx Data Rate (RDR) and Tx Data Rate (TDR). Rx/Tx Data Rate is a multiple of USB2 2.0 HS 480 Mb/s data rates, and is only valid if a eUSB2V2 device is connected (CCS=1). 0 = "USB 2.0 HS" normal HS 480 Mb/s, no eUSB2V2 in use 1 = "HS1" Assymetric eUSB2V2 where this direction runs normal 480Mb/s 2 = "HS2" 960Mb/s ... 10 = "HS10" 4.8 Gb/s, max eUSB2V2 rate PORTLI is Reserved and preserve "RsvdP" for normal USB2 ports Sample output of USB3 port PORTLI: cat /sys/kernel/debug/usb/xhci/0000:00:14.0/ports/port14/portli 0x00000000 LEC=0 RLC=0 TLC=0 Signed-off-by: Rai, Amardeep <amardeep.rai@intel.com> Co-developed-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Link: https://patch.msgid.link/20251119142417.2820519-24-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
121 lines
4.4 KiB
C
121 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* xHCI Host Controller Capability Registers.
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* xHCI Specification Section 5.3, Revision 1.2.
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*/
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#include <linux/bits.h>
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/* hc_capbase - bitmasks */
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/* bits 7:0 - Capability Registers Length */
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#define HC_LENGTH(p) ((p) & 0xff)
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/* bits 15:8 - Rsvd */
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/* bits 31:16 - Host Controller Interface Version Number */
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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/* HCSPARAMS1 - hcs_params1 - bitmasks */
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/* bits 7:0 - Number of Device Slots */
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#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
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#define HCS_SLOTS_MASK 0xff
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/* bits 18:8 - Number of Interrupters, max values is 1024 */
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#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
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/* bits 31:24, Max Ports - max value is 255 */
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#define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff)
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/* HCSPARAMS2 - hcs_params2 - bitmasks */
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/*
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* bits 3:0 - Isochronous Scheduling Threshold, frames or uframes that SW
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* needs to queue transactions ahead of the HW to meet periodic deadlines.
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* - Bits 2:0: Threshold value
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* - Bit 3: Unit indicator
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* - '1': Threshold in Frames
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* - '0': Threshold in Microframes (uframes)
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* Note: 1 Frame = 8 Microframes
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* xHCI specification section 5.3.4.
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*/
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#define HCS_IST_VALUE(p) ((p) & 0x7)
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#define HCS_IST_UNIT BIT(3)
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/* bits 7:4 - Event Ring Segment Table Max, 2^(n) */
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#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
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/* bits 20:8 - Rsvd */
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/* bits 25:21 - Max Scratchpad Buffers (Hi), 5 Most significant bits */
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#define HCS_MAX_SP_HI(p) (((p) >> 21) & 0x1f)
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/* bit 26 - Scratchpad restore, for save/restore HW state */
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/* bits 31:27 - Max Scratchpad Buffers (Lo), 5 Least significant bits */
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#define HCS_MAX_SP_LO(p) (((p) >> 27) & 0x1f)
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#define HCS_MAX_SCRATCHPAD(p) (HCS_MAX_SP_HI(p) << 5 | HCS_MAX_SP_LO(p))
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/* HCSPARAMS3 - hcs_params3 - bitmasks */
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/* bits 7:0 - U1 Device Exit Latency, Max U1 to U0 latency for the roothub ports */
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#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
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/* bits 15:8 - Rsvd */
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/* bits 31:16 - U2 Device Exit Latency, Max U2 to U0 latency for the roothub ports */
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#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
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/* HCCPARAMS1 - hcc_params - bitmasks */
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/* bit 0 - 64-bit Addressing Capability */
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#define HCC_64BIT_ADDR BIT(0)
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/* bit 1 - BW Negotiation Capability */
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#define HCC_BANDWIDTH_NEG BIT(1)
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/* bit 2 - Context Size */
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#define HCC_64BYTE_CONTEXT BIT(2)
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#define CTX_SIZE(_hcc) (_hcc & HCC_64BYTE_CONTEXT ? 64 : 32)
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/* bit 3 - Port Power Control */
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#define HCC_PPC BIT(3)
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/* bit 4 - Port Indicators */
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#define HCS_INDICATOR BIT(4)
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/* bit 5 - Light HC Reset Capability */
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#define HCC_LIGHT_RESET BIT(5)
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/* bit 6 - Latency Tolerance Messaging Capability */
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#define HCC_LTC BIT(6)
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/* bit 7 - No Secondary Stream ID Support */
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#define HCC_NSS BIT(7)
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/* bit 8 - Parse All Event Data */
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/* bit 9 - Short Packet Capability */
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#define HCC_SPC BIT(9)
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/* bit 10 - Stopped EDTLA Capability */
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/* bit 11 - Contiguous Frame ID Capability */
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#define HCC_CFC BIT(11)
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/* bits 15:12 - Max size for Primary Stream Arrays, 2^(n+1) */
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#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
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/* bits 31:16 - xHCI Extended Capabilities Pointer, from PCI base: 2^(n) */
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#define HCC_EXT_CAPS(p) (((p) >> 16) & 0xffff)
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/* DBOFF - db_off - bitmasks */
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/* bits 1:0 - Rsvd */
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/* bits 31:2 - Doorbell Array Offset */
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#define DBOFF_MASK (0xfffffffc)
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/* RTSOFF - run_regs_off - bitmasks */
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/* bits 4:0 - Rsvd */
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/* bits 31:5 - Runtime Register Space Offse */
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#define RTSOFF_MASK (~0x1f)
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/* HCCPARAMS2 - hcc_params2 - bitmasks */
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/* bit 0 - U3 Entry Capability */
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#define HCC2_U3C BIT(0)
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/* bit 1 - Configure Endpoint Command Max Exit Latency Too Large Capability */
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#define HCC2_CMC BIT(1)
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/* bit 2 - Force Save Context Capabilitu */
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#define HCC2_FSC BIT(2)
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/* bit 3 - Compliance Transition Capability, false: compliance is enabled by default */
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#define HCC2_CTC BIT(3)
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/* bit 4 - Large ESIT Payload Capability, true: HC support ESIT payload > 48k */
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#define HCC2_LEC BIT(4)
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/* bit 5 - Configuration Information Capability */
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#define HCC2_CIC BIT(5)
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/* bit 6 - Extended TBC Capability, true: Isoc burst count > 65535 */
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#define HCC2_ETC BIT(6)
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/* bit 7 - Extended TBC TRB Status Capability */
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#define HCC2_ETC_TSC BIT(7)
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/* bit 8 - Get/Set Extended Property Capability */
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#define HCC2_GSC BIT(8)
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/* bit 9 - Virtualization Based Trusted I/O Capability */
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#define HCC2_VTC BIT(9)
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/* bit 10 - Rsvd */
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/* bit 11 - HC support Double BW on a eUSB2 HS ISOC EP */
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#define HCC2_EUSB2_DIC BIT(11)
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/* bit 12 - HC support eUSB2V2 capability */
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#define HCC2_E2V2C BIT(12)
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/* bits 31:13 - Rsvd */
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