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ecab0f3d05
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
v2: - Removed pre/post plane SAGV updates from modeset(Ville)
- Now tracking active pipes in intel_can_enable_sagv(Ville)
v3: - lock global state if active_pipes change as well(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200430195634.7666-1-stanislav.lisovskiy@intel.com
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_BW_H__
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#define __INTEL_BW_H__
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#include <drm/drm_atomic.h>
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#include "intel_display.h"
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#include "intel_global_state.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_bw_state {
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struct intel_global_state base;
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/*
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* Contains a bit mask, used to determine, whether correspondent
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* pipe allows SAGV or not.
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*/
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u8 pipe_sagv_reject;
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unsigned int data_rate[I915_MAX_PIPES];
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u8 num_active_planes[I915_MAX_PIPES];
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/* bitmask of active pipes */
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u8 active_pipes;
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};
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#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
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struct intel_bw_state *
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intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
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struct intel_bw_state *
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intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
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struct intel_bw_state *
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intel_atomic_get_bw_state(struct intel_atomic_state *state);
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void intel_bw_init_hw(struct drm_i915_private *dev_priv);
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int intel_bw_init(struct drm_i915_private *dev_priv);
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int intel_bw_atomic_check(struct intel_atomic_state *state);
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void intel_bw_crtc_update(struct intel_bw_state *bw_state,
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const struct intel_crtc_state *crtc_state);
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#endif /* __INTEL_BW_H__ */
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