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65db7a1f9c
Add helpers to program the 3D LUT registers and arm them. LUT_3D_READY in LUT_3D_CLT is cleared off by the HW once the LUT buffer is loaded into it's internal working RAM. So by the time we try to load/commit new values, we expect it to be cleared off. If not, log an error and return without writing new values. Do it only when writing with MMIO. There is no way to read register within DSB execution. v2: - Add information regarding LUT_3D_READY to commit message (Jani) - Log error instead of a drm_warn and return without committing changes if 3DLUT HW is not ready to accept new values. - Refactor intel_color_crtc_has_3dlut() Also remove Gen10 check (Suraj) v3: - Addressed review comments (Suraj) Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20251203085211.3663374-15-uma.shankar@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
151 lines
2.8 KiB
C
151 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_LIMITS_H__
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#define __INTEL_DISPLAY_LIMITS_H__
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/*
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* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
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* rest have consecutive values and match the enum values of transcoders
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* with a 1:1 transcoder -> pipe mapping.
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*/
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enum pipe {
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INVALID_PIPE = -1,
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PIPE_A = 0,
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PIPE_B,
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PIPE_C,
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PIPE_D,
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_PIPE_EDP,
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I915_MAX_PIPES = _PIPE_EDP
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};
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enum transcoder {
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INVALID_TRANSCODER = -1,
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/*
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* The following transcoders have a 1:1 transcoder -> pipe mapping,
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* keep their values fixed: the code assumes that TRANSCODER_A=0, the
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* rest have consecutive values and match the enum values of the pipes
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* they map to.
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*/
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TRANSCODER_A = PIPE_A,
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TRANSCODER_B = PIPE_B,
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TRANSCODER_C = PIPE_C,
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TRANSCODER_D = PIPE_D,
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/*
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* The following transcoders can map to any pipe, their enum value
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* doesn't need to stay fixed.
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*/
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TRANSCODER_EDP,
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TRANSCODER_DSI_0,
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TRANSCODER_DSI_1,
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TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
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TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
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I915_MAX_TRANSCODERS
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};
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/*
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* Global legacy plane identifier. Valid only for primary/sprite
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* planes on pre-g4x, and only for primary planes on g4x-bdw.
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*/
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enum i9xx_plane_id {
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PLANE_A,
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PLANE_B,
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PLANE_C,
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};
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/*
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* Per-pipe plane identifier.
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* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
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* number of planes per CRTC. Not all platforms really have this many planes,
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* which means some arrays of size I915_MAX_PLANES may have unused entries
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* between the topmost sprite plane and the cursor plane.
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*
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* This is expected to be passed to various register macros
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* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
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*/
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enum plane_id {
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/* skl+ universal plane names */
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PLANE_1,
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PLANE_2,
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PLANE_3,
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PLANE_4,
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PLANE_5,
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PLANE_6,
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PLANE_7,
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PLANE_CURSOR,
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I915_MAX_PLANES,
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/* pre-skl plane names */
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PLANE_PRIMARY = PLANE_1,
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PLANE_SPRITE0,
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PLANE_SPRITE1,
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};
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enum port {
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PORT_NONE = -1,
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PORT_A = 0,
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PORT_B,
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PORT_C,
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PORT_D,
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PORT_E,
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PORT_F,
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PORT_G,
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PORT_H,
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PORT_I,
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/* tgl+ */
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PORT_TC1 = PORT_D,
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PORT_TC2,
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PORT_TC3,
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PORT_TC4,
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PORT_TC5,
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PORT_TC6,
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/* XE_LPD repositions D/E offsets and bitfields */
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PORT_D_XELPD = PORT_TC5,
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PORT_E_XELPD,
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I915_MAX_PORTS
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};
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enum hpd_pin {
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HPD_NONE = 0,
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HPD_TV = HPD_NONE, /* TV is known to be unreliable */
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HPD_CRT,
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HPD_SDVO_B,
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HPD_SDVO_C,
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HPD_PORT_A,
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HPD_PORT_B,
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HPD_PORT_C,
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HPD_PORT_D,
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HPD_PORT_E,
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HPD_PORT_TC1,
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HPD_PORT_TC2,
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HPD_PORT_TC3,
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HPD_PORT_TC4,
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HPD_PORT_TC5,
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HPD_PORT_TC6,
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HPD_NUM_PINS
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};
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enum intel_color_block {
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INTEL_PLANE_CB_PRE_CSC_LUT,
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INTEL_PLANE_CB_CSC,
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INTEL_PLANE_CB_POST_CSC_LUT,
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INTEL_PLANE_CB_3DLUT,
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INTEL_CB_MAX
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};
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#endif /* __INTEL_DISPLAY_LIMITS_H__ */
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