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d84fe2f30b
Add interrupt and exception handler register interface. When exception happens, execute registered exception handler if exists, else report an error. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
211 lines
5.6 KiB
C
211 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SELFTEST_KVM_PROCESSOR_H
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#define SELFTEST_KVM_PROCESSOR_H
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#ifndef __ASSEMBLER__
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#include "ucall_common.h"
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#else
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/* general registers */
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#define zero $r0
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#define ra $r1
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#define tp $r2
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#define sp $r3
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#define a0 $r4
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#define a1 $r5
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#define a2 $r6
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#define a3 $r7
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#define a4 $r8
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#define a5 $r9
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#define a6 $r10
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#define a7 $r11
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#define t0 $r12
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#define t1 $r13
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#define t2 $r14
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#define t3 $r15
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#define t4 $r16
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#define t5 $r17
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#define t6 $r18
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#define t7 $r19
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#define t8 $r20
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#define u0 $r21
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#define fp $r22
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#define s0 $r23
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#define s1 $r24
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#define s2 $r25
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#define s3 $r26
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#define s4 $r27
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#define s5 $r28
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#define s6 $r29
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#define s7 $r30
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#define s8 $r31
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#endif
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/*
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* LoongArch page table entry definition
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* Original header file arch/loongarch/include/asm/loongarch.h
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*/
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#define _PAGE_VALID_SHIFT 0
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#define _PAGE_DIRTY_SHIFT 1
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#define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */
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#define PLV_KERN 0
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#define PLV_USER 3
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#define PLV_MASK 0x3
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#define _CACHE_SHIFT 4 /* 4~5, two bits */
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#define _PAGE_PRESENT_SHIFT 7
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#define _PAGE_WRITE_SHIFT 8
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#define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT)
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#define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT)
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#define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT)
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#define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT)
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#define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT)
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#define __READABLE (_PAGE_VALID)
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#define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE)
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/* Coherent Cached */
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#define _CACHE_CC BIT_ULL(_CACHE_SHIFT)
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#define PS_4K 0x0000000c
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#define PS_16K 0x0000000e
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#define PS_64K 0x00000010
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#define PS_DEFAULT_SIZE PS_16K
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/* LoongArch Basic CSR registers */
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#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
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#define CSR_CRMD_PG_SHIFT 4
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#define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT)
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#define CSR_CRMD_IE_SHIFT 2
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#define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT)
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#define CSR_CRMD_PLV_SHIFT 0
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#define CSR_CRMD_PLV_WIDTH 2
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#define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT)
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#define PLV_MASK 0x3
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#define LOONGARCH_CSR_PRMD 0x1
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#define LOONGARCH_CSR_EUEN 0x2
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#define LOONGARCH_CSR_ECFG 0x4
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#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
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#define CSR_ESTAT_EXC_SHIFT 16
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#define CSR_ESTAT_EXC_WIDTH 6
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#define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT)
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#define EXCCODE_INT 0 /* Interrupt */
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#define INT_TI 11 /* Timer interrupt*/
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#define LOONGARCH_CSR_ERA 0x6 /* ERA */
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#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
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#define LOONGARCH_CSR_EENTRY 0xc
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#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */
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#define CSR_TLBIDX_PS_SHIFT 24
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#define CSR_TLBIDX_PS_WIDTH 6
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#define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT)
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#define CSR_TLBIDX_SIZEM 0x3f000000
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#define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
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#define LOONGARCH_CSR_ASID 0x18 /* ASID */
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#define LOONGARCH_CSR_PGDL 0x19
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#define LOONGARCH_CSR_PGDH 0x1a
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/* Page table base */
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#define LOONGARCH_CSR_PGD 0x1b
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#define LOONGARCH_CSR_PWCTL0 0x1c
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#define LOONGARCH_CSR_PWCTL1 0x1d
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#define LOONGARCH_CSR_STLBPGSIZE 0x1e
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#define LOONGARCH_CSR_CPUID 0x20
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#define LOONGARCH_CSR_KS0 0x30
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#define LOONGARCH_CSR_KS1 0x31
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#define LOONGARCH_CSR_TMID 0x40
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#define LOONGARCH_CSR_TCFG 0x41
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/* TLB refill exception entry */
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#define LOONGARCH_CSR_TLBRENTRY 0x88
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#define LOONGARCH_CSR_TLBRSAVE 0x8b
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#define LOONGARCH_CSR_TLBREHI 0x8e
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#define CSR_TLBREHI_PS_SHIFT 0
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#define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT)
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__( \
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"csrrd %[val], %[reg]\n\t" \
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: [val] "=r" (__v) \
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: [reg] "i" (csr) \
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: "memory"); \
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__v; \
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})
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#define csr_write(v, csr) \
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({ \
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register unsigned long __v = v; \
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__asm__ __volatile__ ( \
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"csrwr %[val], %[reg]\n\t" \
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: [val] "+r" (__v) \
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: [reg] "i" (csr) \
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: "memory"); \
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__v; \
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})
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#define EXREGS_GPRS (32)
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#ifndef __ASSEMBLER__
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void handle_tlb_refill(void);
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void handle_exception(void);
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struct ex_regs {
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unsigned long regs[EXREGS_GPRS];
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unsigned long pc;
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unsigned long estat;
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unsigned long badv;
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unsigned long prmd;
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};
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#define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc)
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#define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat)
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#define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv)
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#define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd)
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#define EXREGS_SIZE sizeof(struct ex_regs)
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#define VECTOR_NUM 64
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typedef void(*handler_fn)(struct ex_regs *);
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struct handlers {
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handler_fn exception_handlers[VECTOR_NUM];
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};
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void vm_init_descriptor_tables(struct kvm_vm *vm);
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void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn handler);
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static inline void cpu_relax(void)
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{
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asm volatile("nop" ::: "memory");
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}
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static inline void local_irq_enable(void)
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{
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unsigned int flags = CSR_CRMD_IE;
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register unsigned int mask asm("$t0") = CSR_CRMD_IE;
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__asm__ __volatile__(
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"csrxchg %[val], %[mask], %[reg]\n\t"
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: [val] "+r" (flags)
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: [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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}
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static inline void local_irq_disable(void)
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{
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unsigned int flags = 0;
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register unsigned int mask asm("$t0") = CSR_CRMD_IE;
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__asm__ __volatile__(
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"csrxchg %[val], %[mask], %[reg]\n\t"
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: [val] "+r" (flags)
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: [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
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: "memory");
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}
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#else
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#define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8)
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#define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8)
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#define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8)
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#define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8)
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#define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8)
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#endif
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#endif /* SELFTEST_KVM_PROCESSOR_H */
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