David Abdurachmanov 7ede12b01b riscv: dts: fu740: fix cache-controller interrupts ...

The order of interrupt numbers is incorrect.

The order for FU740 is: DirError, DataError, DataFail, DirFail

From SiFive FU740-C000 Manual:
19 - L2 Cache DirError
20 - L2 Cache DirFail
21 - L2 Cache DataError
22 - L2 Cache DataFail

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

2021-06-19 00:11:53 -07:00

..

boot

riscv: dts: fu740: fix cache-controller interrupts

2021-06-19 00:11:53 -07:00

configs

RISC-V: Enable Microchip PolarFire ICICLE SoC

2021-04-26 08:31:32 -07:00

errata

riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled

2021-06-01 21:16:41 -07:00

include

riscv: Ensure BPF_JIT_REGION_START aligned with PMD size

2021-06-18 21:10:05 -07:00

kernel

riscv: xip: support runtime trap patching

2021-06-10 16:16:06 -07:00

lib

riscv: Add support for function error injection

2021-01-14 15:09:09 -08:00

mm

riscv: Ensure BPF_JIT_REGION_START aligned with PMD size

2021-06-18 21:10:05 -07:00

net

riscv: bpf: Avoid breaking W^X

2021-04-26 08:25:14 -07:00

Kbuild

riscv: Allow device trees to be built into the kernel

2020-05-18 11:38:05 -07:00

Kconfig

riscv: code patching only works on !XIP_KERNEL

2021-06-10 16:33:50 -07:00

Kconfig.debug

RISC-V: Remove EARLY_PRINTK support

2018-12-17 10:23:46 -08:00

Kconfig.erratas

riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y

2021-05-06 09:40:13 -07:00

Kconfig.socs

riscv: sifive: fix Kconfig errata warning

2021-06-12 17:20:50 -07:00

Makefile

riscv32: Use medany C model for modules

2021-06-12 17:20:49 -07:00