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Speculative prefetches from CPU to GPU memory until the GPU is ready after reset can cause harmless corrected RAS events to be logged on Grace systems. It is thus preferred that the mapping not be re-established until the GPU is ready post reset. The GPU readiness can be checked through BAR0 registers similar to the checking at the time of device probe. It can take several seconds for the GPU to be ready. So it is desirable that the time overlaps as much of the VM startup as possible to reduce impact on the VM bootup time. The GPU readiness state is thus checked on the first fault/huge_fault request or read/write access which amortizes the GPU readiness time. The first fault and read/write checks the GPU state when the reset_done flag - which denotes whether the GPU has just been reset. The memory_lock is taken across map/access to avoid races with GPU reset. Also check if the memory is enabled, before waiting for GPU to be ready. Otherwise the readiness check would block for 30s. Lastly added PM handling wrapping on read/write access. Cc: Shameer Kolothum <skolothumtho@nvidia.com> Cc: Alex Williamson <alex@shazbot.org> Cc: Jason Gunthorpe <jgg@ziepe.ca> Cc: Vikram Sethi <vsethi@nvidia.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com> Suggested-by: Alex Williamson <alex@shazbot.org> Signed-off-by: Ankit Agrawal <ankita@nvidia.com> Link: https://lore.kernel.org/r/20251127170632.3477-7-ankita@nvidia.com Signed-off-by: Alex Williamson <alex@shazbot.org>
137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VFIO_PCI_PRIV_H
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#define VFIO_PCI_PRIV_H
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#include <linux/vfio_pci_core.h>
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/* Special capability IDs predefined access */
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#define PCI_CAP_ID_INVALID 0xFF /* default raw access */
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#define PCI_CAP_ID_INVALID_VIRT 0xFE /* default virt access */
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/* Cap maximum number of ioeventfds per device (arbitrary) */
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#define VFIO_PCI_IOEVENTFD_MAX 1000
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struct vfio_pci_ioeventfd {
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struct list_head next;
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struct vfio_pci_core_device *vdev;
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struct virqfd *virqfd;
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void __iomem *addr;
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uint64_t data;
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loff_t pos;
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int bar;
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int count;
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bool test_mem;
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};
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bool vfio_pci_intx_mask(struct vfio_pci_core_device *vdev);
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void vfio_pci_intx_unmask(struct vfio_pci_core_device *vdev);
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int vfio_pci_eventfd_replace_locked(struct vfio_pci_core_device *vdev,
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struct vfio_pci_eventfd __rcu **peventfd,
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struct eventfd_ctx *ctx);
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int vfio_pci_set_irqs_ioctl(struct vfio_pci_core_device *vdev, uint32_t flags,
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unsigned index, unsigned start, unsigned count,
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void *data);
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ssize_t vfio_pci_config_rw(struct vfio_pci_core_device *vdev, char __user *buf,
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size_t count, loff_t *ppos, bool iswrite);
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ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf,
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size_t count, loff_t *ppos, bool iswrite);
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#ifdef CONFIG_VFIO_PCI_VGA
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ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev, char __user *buf,
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size_t count, loff_t *ppos, bool iswrite);
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#else
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static inline ssize_t vfio_pci_vga_rw(struct vfio_pci_core_device *vdev,
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char __user *buf, size_t count,
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loff_t *ppos, bool iswrite)
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{
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return -EINVAL;
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}
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#endif
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int vfio_pci_ioeventfd(struct vfio_pci_core_device *vdev, loff_t offset,
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uint64_t data, int count, int fd);
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int vfio_pci_init_perm_bits(void);
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void vfio_pci_uninit_perm_bits(void);
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int vfio_config_init(struct vfio_pci_core_device *vdev);
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void vfio_config_free(struct vfio_pci_core_device *vdev);
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int vfio_pci_set_power_state(struct vfio_pci_core_device *vdev,
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pci_power_t state);
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void vfio_pci_zap_and_down_write_memory_lock(struct vfio_pci_core_device *vdev);
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u16 vfio_pci_memory_lock_and_enable(struct vfio_pci_core_device *vdev);
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void vfio_pci_memory_unlock_and_restore(struct vfio_pci_core_device *vdev,
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u16 cmd);
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#ifdef CONFIG_VFIO_PCI_IGD
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bool vfio_pci_is_intel_display(struct pci_dev *pdev);
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int vfio_pci_igd_init(struct vfio_pci_core_device *vdev);
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#else
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static inline bool vfio_pci_is_intel_display(struct pci_dev *pdev)
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{
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return false;
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}
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static inline int vfio_pci_igd_init(struct vfio_pci_core_device *vdev)
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{
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return -ENODEV;
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}
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#endif
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#ifdef CONFIG_VFIO_PCI_ZDEV_KVM
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int vfio_pci_info_zdev_add_caps(struct vfio_pci_core_device *vdev,
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struct vfio_info_cap *caps);
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int vfio_pci_zdev_open_device(struct vfio_pci_core_device *vdev);
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void vfio_pci_zdev_close_device(struct vfio_pci_core_device *vdev);
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#else
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static inline int vfio_pci_info_zdev_add_caps(struct vfio_pci_core_device *vdev,
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struct vfio_info_cap *caps)
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{
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return -ENODEV;
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}
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static inline int vfio_pci_zdev_open_device(struct vfio_pci_core_device *vdev)
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{
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return 0;
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}
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static inline void vfio_pci_zdev_close_device(struct vfio_pci_core_device *vdev)
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{}
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#endif
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static inline bool vfio_pci_is_vga(struct pci_dev *pdev)
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{
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return (pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA;
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}
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#ifdef CONFIG_VFIO_PCI_DMABUF
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int vfio_pci_core_feature_dma_buf(struct vfio_pci_core_device *vdev, u32 flags,
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struct vfio_device_feature_dma_buf __user *arg,
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size_t argsz);
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void vfio_pci_dma_buf_cleanup(struct vfio_pci_core_device *vdev);
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void vfio_pci_dma_buf_move(struct vfio_pci_core_device *vdev, bool revoked);
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#else
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static inline int
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vfio_pci_core_feature_dma_buf(struct vfio_pci_core_device *vdev, u32 flags,
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struct vfio_device_feature_dma_buf __user *arg,
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size_t argsz)
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{
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return -ENOTTY;
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}
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static inline void vfio_pci_dma_buf_cleanup(struct vfio_pci_core_device *vdev)
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{
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}
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static inline void vfio_pci_dma_buf_move(struct vfio_pci_core_device *vdev,
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bool revoked)
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{
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}
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#endif
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#endif
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