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b3fd04e23f
Unify the naming of the existing GPU OPP table nodes found in the RK3588
and RK3588J SoC dtsi files with the other SoC's GPU OPP nodes, following
the more "modern" node naming scheme.
Fixes: a7b2070505 ("arm64: dts: rockchip: Split GPU OPPs of RK3588 and RK3588j")
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
[opp-table also is way too generic on systems with like 4-5 opp-tables]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
130 lines
2.6 KiB
Plaintext
130 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "rk3588-extra.dtsi"
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/ {
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cluster0_opp_table: opp-table-cluster0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <750000 750000 950000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-1296000000 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-microvolt = <775000 775000 950000>;
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clock-latency-ns = <40000>;
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};
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};
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cluster1_opp_table: opp-table-cluster1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <750000 750000 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <762500 762500 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <787500 787500 950000>;
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clock-latency-ns = <40000>;
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};
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};
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cluster2_opp_table: opp-table-cluster2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <750000 750000 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <762500 762500 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <787500 787500 950000>;
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clock-latency-ns = <40000>;
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};
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};
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gpu_opp_table: opp-table-gpu {
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compatible = "operating-points-v2";
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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opp-700000000 {
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opp-hz = /bits/ 64 <700000000>;
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opp-microvolt = <750000 750000 850000>;
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};
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};
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};
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&cpu_b0 {
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operating-points-v2 = <&cluster1_opp_table>;
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};
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&cpu_b1 {
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operating-points-v2 = <&cluster1_opp_table>;
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};
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&cpu_b2 {
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operating-points-v2 = <&cluster2_opp_table>;
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};
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&cpu_b3 {
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operating-points-v2 = <&cluster2_opp_table>;
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};
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&cpu_l0 {
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operating-points-v2 = <&cluster0_opp_table>;
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};
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&cpu_l1 {
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operating-points-v2 = <&cluster0_opp_table>;
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};
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&cpu_l2 {
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operating-points-v2 = <&cluster0_opp_table>;
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};
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&cpu_l3 {
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operating-points-v2 = <&cluster0_opp_table>;
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};
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&gpu {
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operating-points-v2 = <&gpu_opp_table>;
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};
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