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linux/arch/arm64/boot/dts/rockchip/rk3576.dtsi
Chukun Pan 264152a97e arm64: dts: rockchip: drop reset from rk3576 i2c9 node 
The reset property is not part of the binding, so drop it.
It is also not used by the driver, so it was likely copied
from some vendor-kernel node.

Fixes: 57b1ce9039 ("arm64: dts: rockchip: Add rk3576 SoC base DT")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://patch.msgid.link/20251101140101.302229-1-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-11-13 23:55:53 +01:00

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rockchip,rk3576-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rockchip,rk3576-power.h>
#include <dt-bindings/reset/rockchip,rk3576-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3576";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
serial10 = &uart10;
serial11 = &uart11;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
};
xin32k: clock-xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
};
xin24m: clock-xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "xin24m";
};
spll: clock-spll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <702000000>;
clock-output-names = "spll";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu_l0>;
};
core1 {
cpu = <&cpu_l1>;
};
core2 {
cpu = <&cpu_l2>;
};
core3 {
cpu = <&cpu_l3>;
};
};
cluster1 {
core0 {
cpu = <&cpu_b0>;
};
core1 {
cpu = <&cpu_b1>;
};
core2 {
cpu = <&cpu_b2>;
};
core3 {
cpu = <&cpu_b3>;
};
};
};
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
dynamic-power-coefficient = <120>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_l1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_l2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_l3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
capacity-dmips-mhz = <485>;
clocks = <&scmi_clk SCMI_ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_b0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
dynamic-power-coefficient = <320>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_b1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_b2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
cpu_b3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
clocks = <&scmi_clk SCMI_ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
#cooling-cells = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <120>;
exit-latency-us = <250>;
min-residency-us = <900>;
local-timer-stop;
};
};
};
cluster0_opp_table: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <725000 725000 950000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <750000 750000 950000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <825000 825000 950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <900000 900000 950000>;
clock-latency-ns = <40000>;
};
};
cluster1_opp_table: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <700000 700000 950000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <712500 712500 950000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <737500 737500 950000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <800000 800000 950000>;
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <862500 862500 950000>;
clock-latency-ns = <40000>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <925000 925000 950000>;
clock-latency-ns = <40000>;
};
};
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <700000 700000 850000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <700000 700000 850000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <700000 700000 850000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <700000 700000 850000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <725000 725000 850000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <775000 775000 850000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <825000 825000 850000>;
};
opp-950000000 {
opp-hz = /bits/ 64 <950000000>;
opp-microvolt = <850000 850000 850000>;
};
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x82000010>;
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
hdmi_sound: hdmi-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "HDMI";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
status = "disabled";
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
simple-audio-card,cpu {
sound-dai = <&sai6>;
};
};
pinctrl: pinctrl {
compatible = "rockchip,rk3576-pinctrl";
rockchip,grf = <&ioc_grf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@27320000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x27320000 0x0 0x200>;
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio1: gpio@2ae10000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae10000 0x0 0x200>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio2: gpio@2ae20000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae20000 0x0 0x200>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio3: gpio@2ae30000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae30000 0x0 0x200>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
gpio4: gpio@2ae40000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0x2ae40000 0x0 0x200>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
gpio-ranges = <&pinctrl 0 128 32>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
};
pmu_a53: pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
};
pmu_a72: pmu-a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
thermal_zones: thermal-zones {
/* sensor near the center of the SoC */
package_thermal: package-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsadc 0>;
trips {
package_crit: package-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
/* sensor for cluster1 (big Cortex-A72 cores) */
bigcore_thermal: bigcore-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsadc 1>;
trips {
bigcore_alert: bigcore-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
bigcore_crit: bigcore-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&bigcore_alert>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
/* sensor for cluster0 (little Cortex-A53 cores) */
littlecore_thermal: littlecore-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsadc 2>;
trips {
littlecore_alert: littlecore-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
littlecore_crit: littlecore-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&littlecore_alert>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu_thermal: gpu-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsadc 3>;
trips {
gpu_alert: gpu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit: gpu-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert>;
cooling-device =
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
npu_thermal: npu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsadc 4>;
trips {
npu_crit: npu-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
ddr_thermal: ddr-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsadc 5>;
trips {
ddr_crit: ddr-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie0: pcie@22000000 {
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
reg = <0x0 0x22000000 0x0 0x00400000>,
<0x0 0x2a200000 0x0 0x00010000>,
<0x0 0x20000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x0 0xf>;
clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
<&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
<&cru CLK_PCIE0_AUX>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
linux,pci-domain = <0>;
max-link-speed = <2>;
num-ib-windows = <8>;
num-viewport = <8>;
num-ob-windows = <2>;
num-lanes = <1>;
phys = <&combphy0_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3576_PD_PHP>;
ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
reset-names = "pwr", "pipe";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie0_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
};
};
pcie1: pcie@22400000 {
compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
reg = <0x0 0x22400000 0x0 0x00400000>,
<0x0 0x2a210000 0x0 0x00010000>,
<0x0 0x21000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
<&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
<&cru CLK_PCIE1_AUX>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
linux,pci-domain = <1>;
max-link-speed = <2>;
num-ib-windows = <8>;
num-viewport = <8>;
num-ob-windows = <2>;
num-lanes = <1>;
phys = <&combphy1_psu PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3576_PD_SUBPHP>;
ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
reset-names = "pwr", "pipe";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
pcie1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
};
};
usb_drd0_dwc3: usb@23000000 {
compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
reg = <0x0 0x23000000 0x0 0x400000>;
clocks = <&cru CLK_REF_USB3OTG0>,
<&cru CLK_SUSPEND_USB3OTG0>,
<&cru ACLK_USB3OTG0>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_USB>;
resets = <&cru SRST_A_USB3OTG0>;
dr_mode = "otg";
phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
usb_drd1_dwc3: usb@23400000 {
compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
reg = <0x0 0x23400000 0x0 0x400000>;
clocks = <&cru CLK_REF_USB3OTG1>,
<&cru CLK_SUSPEND_USB3OTG1>,
<&cru ACLK_USB3OTG1>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_PHP>;
resets = <&cru SRST_A_USB3OTG1>;
dr_mode = "otg";
phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
dma-coherent;
status = "disabled";
};
sys_grf: syscon@2600a000 {
compatible = "rockchip,rk3576-sys-grf", "syscon";
reg = <0x0 0x2600a000 0x0 0x2000>;
};
bigcore_grf: syscon@2600c000 {
compatible = "rockchip,rk3576-bigcore-grf", "syscon";
reg = <0x0 0x2600c000 0x0 0x2000>;
};
litcore_grf: syscon@2600e000 {
compatible = "rockchip,rk3576-litcore-grf", "syscon";
reg = <0x0 0x2600e000 0x0 0x2000>;
};
cci_grf: syscon@26010000 {
compatible = "rockchip,rk3576-cci-grf", "syscon";
reg = <0x0 0x26010000 0x0 0x2000>;
};
gpu_grf: syscon@26016000 {
compatible = "rockchip,rk3576-gpu-grf", "syscon";
reg = <0x0 0x26016000 0x0 0x2000>;
};
npu_grf: syscon@26018000 {
compatible = "rockchip,rk3576-npu-grf", "syscon";
reg = <0x0 0x26018000 0x0 0x2000>;
};
vo0_grf: syscon@2601a000 {
compatible = "rockchip,rk3576-vo0-grf", "syscon";
reg = <0x0 0x2601a000 0x0 0x2000>;
};
usb_grf: syscon@2601e000 {
compatible = "rockchip,rk3576-usb-grf", "syscon";
reg = <0x0 0x2601e000 0x0 0x1000>;
};
php_grf: syscon@26020000 {
compatible = "rockchip,rk3576-php-grf", "syscon";
reg = <0x0 0x26020000 0x0 0x2000>;
};
pmu0_grf: syscon@26024000 {
compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
reg = <0x0 0x26024000 0x0 0x1000>;
};
pmu1_grf: syscon@26026000 {
compatible = "rockchip,rk3576-pmu1-grf", "syscon";
reg = <0x0 0x26026000 0x0 0x1000>;
};
pipe_phy0_grf: syscon@26028000 {
compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
reg = <0x0 0x26028000 0x0 0x2000>;
};
pipe_phy1_grf: syscon@2602a000 {
compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
reg = <0x0 0x2602a000 0x0 0x2000>;
};
usbdpphy_grf: syscon@2602c000 {
compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
reg = <0x0 0x2602c000 0x0 0x2000>;
};
usb2phy_grf: syscon@2602e000 {
compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0x2602e000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy0: usb2-phy@0 {
compatible = "rockchip,rk3576-usb2phy";
reg = <0x0 0x10>;
resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
reset-names = "phy", "apb";
clocks = <&cru CLK_PHY_REF_SRC>,
<&cru ACLK_MMU2>,
<&cru ACLK_SLV_MMU2>;
clock-names = "phyclk", "aclk", "aclk_slv";
clock-output-names = "usb480m_phy0";
#clock-cells = <0>;
status = "disabled";
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id", "linestate";
status = "disabled";
};
};
u2phy1: usb2-phy@2000 {
compatible = "rockchip,rk3576-usb2phy";
reg = <0x2000 0x10>;
resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
reset-names = "phy", "apb";
clocks = <&cru CLK_PHY_REF_SRC>,
<&cru ACLK_MMU1>,
<&cru ACLK_SLV_MMU1>;
clock-names = "phyclk", "aclk", "aclk_slv";
clock-output-names = "usb480m_phy1";
#clock-cells = <0>;
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id", "linestate";
status = "disabled";
};
};
};
hdptxphy_grf: syscon@26032000 {
compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
reg = <0x0 0x26032000 0x0 0x100>;
};
mipidcphy_grf: syscon@26034000 {
compatible = "rockchip,rk3576-dcphy-grf", "syscon";
reg = <0x0 0x26034000 0x0 0x2000>;
clocks = <&cru PCLK_PMUPHY_ROOT>;
};
vo1_grf: syscon@26036000 {
compatible = "rockchip,rk3576-vo1-grf", "syscon";
reg = <0x0 0x26036000 0x0 0x100>;
clocks = <&cru PCLK_VO1_ROOT>;
};
sdgmac_grf: syscon@26038000 {
compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
reg = <0x0 0x26038000 0x0 0x1000>;
};
ioc_grf: syscon@26040000 {
compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
reg = <0x0 0x26040000 0x0 0xc000>;
};
cru: clock-controller@27200000 {
compatible = "rockchip,rk3576-cru";
reg = <0x0 0x27200000 0x0 0x50000>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru CLK_AUDIO_FRAC_1_SRC>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
<&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>,
<&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>,
<&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>,
<&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>,
<&cru ACLK_PHP_ROOT>;
assigned-clock-parents = <&cru PLL_AUPLL>;
assigned-clock-rates =
<0>,
<1188000000>, <1000000000>,
<786432000>, <18432000>,
<96000000>, <128000000>,
<45158400>, <49152000>,
<500000000>, <250000000>,
<100000000>, <500000000>,
<250000000>;
};
i2c0: i2c@27300000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x27300000 0x0 0x1000>;
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart1: serial@27310000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x27310000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 8>, <&dmac0 9>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer>;
status = "disabled";
};
pmu: power-management@27380000 {
compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
reg = <0x0 0x27380000 0x0 0x800>;
power: power-controller {
compatible = "rockchip,rk3576-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_NPU {
reg = <RK3576_PD_NPU>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_NPUTOP {
reg = <RK3576_PD_NPUTOP>;
clocks = <&cru ACLK_RKNN0>,
<&cru ACLK_RKNN1>,
<&cru ACLK_RKNN_CBUF>,
<&cru CLK_RKNN_DSU0>,
<&cru HCLK_RKNN_CBUF>,
<&cru HCLK_RKNN_ROOT>,
<&cru HCLK_NPU_CM0_ROOT>,
<&cru PCLK_NPUTOP_ROOT>;
pm_qos = <&qos_npu_mcu>,
<&qos_npu_nsp0>,
<&qos_npu_nsp1>,
<&qos_npu_m0ro>,
<&qos_npu_m1ro>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_NPU0 {
reg = <RK3576_PD_NPU0>;
clocks = <&cru HCLK_RKNN_ROOT>,
<&cru ACLK_RKNN0>;
pm_qos = <&qos_npu_m0>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_NPU1 {
reg = <RK3576_PD_NPU1>;
clocks = <&cru HCLK_RKNN_ROOT>,
<&cru ACLK_RKNN1>;
pm_qos = <&qos_npu_m1>;
#power-domain-cells = <0>;
};
};
};
power-domain@RK3576_PD_GPU {
reg = <RK3576_PD_GPU>;
clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_NVM {
reg = <RK3576_PD_NVM>;
clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>;
pm_qos = <&qos_emmc>,
<&qos_fspi0>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_SDGMAC {
reg = <RK3576_PD_SDGMAC>;
clocks = <&cru ACLK_HSGPIO>,
<&cru ACLK_GMAC0>,
<&cru ACLK_GMAC1>,
<&cru CCLK_SRC_SDIO>,
<&cru CCLK_SRC_SDMMC0>,
<&cru HCLK_HSGPIO>,
<&cru HCLK_SDIO>,
<&cru HCLK_SDMMC0>,
<&cru PCLK_SDGMAC_ROOT>;
pm_qos = <&qos_fspi1>,
<&qos_gmac0>,
<&qos_gmac1>,
<&qos_sdio>,
<&qos_sdmmc>,
<&qos_flexbus>;
#power-domain-cells = <0>;
};
};
power-domain@RK3576_PD_PHP {
reg = <RK3576_PD_PHP>;
clocks = <&cru ACLK_PHP_ROOT>,
<&cru PCLK_PHP_ROOT>,
<&cru ACLK_MMU0>,
<&cru ACLK_MMU1>;
pm_qos = <&qos_mmu0>,
<&qos_mmu1>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_SUBPHP {
reg = <RK3576_PD_SUBPHP>;
#power-domain-cells = <0>;
};
};
power-domain@RK3576_PD_AUDIO {
reg = <RK3576_PD_AUDIO>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_VEPU1 {
reg = <RK3576_PD_VEPU1>;
clocks = <&cru ACLK_VEPU1>,
<&cru HCLK_VEPU1>;
pm_qos = <&qos_vepu1>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_VPU {
reg = <RK3576_PD_VPU>;
clocks = <&cru ACLK_EBC>,
<&cru HCLK_EBC>,
<&cru ACLK_JPEG>,
<&cru HCLK_JPEG>,
<&cru ACLK_RGA2E_0>,
<&cru HCLK_RGA2E_0>,
<&cru ACLK_RGA2E_1>,
<&cru HCLK_RGA2E_1>,
<&cru ACLK_VDPP>,
<&cru HCLK_VDPP>;
pm_qos = <&qos_ebc>,
<&qos_jpeg>,
<&qos_rga0>,
<&qos_rga1>,
<&qos_vdpp>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_VDEC {
reg = <RK3576_PD_VDEC>;
clocks = <&cru ACLK_RKVDEC_ROOT>,
<&cru HCLK_RKVDEC>;
pm_qos = <&qos_rkvdec>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_VI {
reg = <RK3576_PD_VI>;
clocks = <&cru ACLK_VICAP>,
<&cru HCLK_VICAP>,
<&cru DCLK_VICAP>,
<&cru ACLK_VI_ROOT>,
<&cru HCLK_VI_ROOT>,
<&cru PCLK_VI_ROOT>,
<&cru CLK_ISP_CORE>,
<&cru ACLK_ISP>,
<&cru HCLK_ISP>,
<&cru CLK_CORE_VPSS>,
<&cru ACLK_VPSS>,
<&cru HCLK_VPSS>;
pm_qos = <&qos_isp_mro>,
<&qos_isp_mwo>,
<&qos_vicap_m0>,
<&qos_vpss_mro>,
<&qos_vpss_mwo>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_VEPU0 {
reg = <RK3576_PD_VEPU0>;
clocks = <&cru ACLK_VEPU0>,
<&cru HCLK_VEPU0>;
pm_qos = <&qos_vepu0>;
#power-domain-cells = <0>;
};
};
power-domain@RK3576_PD_VOP {
reg = <RK3576_PD_VOP>;
clocks = <&cru ACLK_VOP>,
<&cru HCLK_VOP>,
<&cru HCLK_VOP_ROOT>,
<&cru PCLK_VOP_ROOT>;
pm_qos = <&qos_vop_m0>,
<&qos_vop_m1ro>;
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3576_PD_USB {
reg = <RK3576_PD_USB>;
clocks = <&cru PCLK_PHP_ROOT>,
<&cru ACLK_USB_ROOT>,
<&cru ACLK_MMU2>,
<&cru ACLK_SLV_MMU2>,
<&cru ACLK_UFS_SYS>;
pm_qos = <&qos_mmu2>,
<&qos_ufshc>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_VO0 {
reg = <RK3576_PD_VO0>;
clocks = <&cru ACLK_HDCP0>,
<&cru HCLK_HDCP0>,
<&cru ACLK_VO0_ROOT>,
<&cru PCLK_VO0_ROOT>,
<&cru HCLK_VOP_ROOT>;
pm_qos = <&qos_hdcp0>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_VO1 {
reg = <RK3576_PD_VO1>;
clocks = <&cru ACLK_HDCP1>,
<&cru HCLK_HDCP1>,
<&cru ACLK_VO1_ROOT>,
<&cru PCLK_VO1_ROOT>,
<&cru HCLK_VOP_ROOT>;
pm_qos = <&qos_hdcp1>;
#power-domain-cells = <0>;
};
};
};
};
gpu: gpu@27800000 {
compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
reg = <0x0 0x27800000 0x0 0x200000>;
assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
assigned-clock-rates = <198000000>;
clocks = <&cru CLK_GPU>;
clock-names = "core";
dynamic-power-coefficient = <1625>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3576_PD_GPU>;
#cooling-cells = <2>;
status = "disabled";
};
vop: vop@27d00000 {
compatible = "rockchip,rk3576-vop";
reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
reg-names = "vop", "gamma-lut";
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys",
"vp0",
"vp1",
"vp2";
clocks = <&cru ACLK_VOP>,
<&cru HCLK_VOP>,
<&cru DCLK_VP0>,
<&cru DCLK_VP1>,
<&cru DCLK_VP2>,
<&hdptxphy>;
clock-names = "aclk",
"hclk",
"dclk_vp0",
"dclk_vp1",
"dclk_vp2",
"pll_hdmiphy0";
iommus = <&vop_mmu>;
power-domains = <&power RK3576_PD_VOP>;
rockchip,grf = <&sys_grf>;
rockchip,pmu = <&pmu>;
status = "disabled";
vop_out: ports {
#address-cells = <1>;
#size-cells = <0>;
vp0: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
vp1: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
vp2: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
};
};
vop_mmu: iommu@27d07e00 {
compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3576_PD_VOP>;
status = "disabled";
};
sai5: sai@27d40000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27d40000 0x0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac2 3>;
dma-names = "rx";
power-domains = <&power RK3576_PD_VO0>;
resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
reset-names = "m", "h";
rockchip,sai-rx-route = <0 1 2 3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI5";
status = "disabled";
};
sai6: sai@27d50000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27d50000 0x0 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac2 4>, <&dmac2 5>;
dma-names = "tx", "rx";
power-domains = <&power RK3576_PD_VO0>;
resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
reset-names = "m", "h";
rockchip,sai-rx-route = <0 1 2 3>;
rockchip,sai-tx-route = <0 1 2 3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI6";
status = "disabled";
};
dsi: dsi@27d80000 {
compatible = "rockchip,rk3576-mipi-dsi2";
reg = <0x0 0x27d80000 0x0 0x10000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
clock-names = "pclk", "sys";
power-domains = <&power RK3576_PD_VO0>;
resets = <&cru SRST_P_DSIHOST0>;
reset-names = "apb";
phys = <&mipidcphy PHY_TYPE_DPHY>;
phy-names = "dcphy";
rockchip,grf = <&vo0_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dsi_in: port@0 {
reg = <0>;
};
dsi_out: port@1 {
reg = <1>;
};
};
};
hdmi: hdmi@27da0000 {
compatible = "rockchip,rk3576-dw-hdmi-qp";
reg = <0x0 0x27da0000 0x0 0x20000>;
clocks = <&cru PCLK_HDMITX0>,
<&cru CLK_HDMITX0_EARC>,
<&cru CLK_HDMITX0_REF>,
<&cru MCLK_SAI6_8CH>,
<&cru CLK_HDMITXHDP>,
<&cru HCLK_VO0_ROOT>;
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
phys = <&hdptxphy>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
power-domains = <&power RK3576_PD_VO0>;
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
reset-names = "ref", "hdp";
rockchip,grf = <&ioc_grf>;
rockchip,vo-grf = <&vo0_grf>;
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
sai7: sai@27ed0000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27ed0000 0x0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac2 19>;
dma-names = "tx";
power-domains = <&power RK3576_PD_VO1>;
resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>;
reset-names = "m", "h";
rockchip,sai-tx-route = <0 1 2 3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI7";
status = "disabled";
};
sai8: sai@27ee0000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27ee0000 0x0 0x1000>;
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac1 7>;
dma-names = "tx";
power-domains = <&power RK3576_PD_VO1>;
resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>;
reset-names = "m", "h";
rockchip,sai-tx-route = <0 1 2 3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI8";
status = "disabled";
};
sai9: sai@27ef0000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x27ef0000 0x0 0x1000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac0 26>;
dma-names = "tx";
power-domains = <&power RK3576_PD_VO1>;
resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>;
reset-names = "m", "h";
rockchip,sai-tx-route = <0 1 2 3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI9";
status = "disabled";
};
qos_hdcp1: qos@27f02000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f02000 0x0 0x20>;
};
qos_fspi1: qos@27f04000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f04000 0x0 0x20>;
};
qos_gmac0: qos@27f04080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f04080 0x0 0x20>;
};
qos_gmac1: qos@27f04100 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f04100 0x0 0x20>;
};
qos_sdio: qos@27f04180 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f04180 0x0 0x20>;
};
qos_sdmmc: qos@27f04200 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f04200 0x0 0x20>;
};
qos_flexbus: qos@27f04280 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f04280 0x0 0x20>;
};
qos_gpu: qos@27f05000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f05000 0x0 0x20>;
};
qos_vepu1: qos@27f06000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f06000 0x0 0x20>;
};
qos_npu_mcu: qos@27f08000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f08000 0x0 0x20>;
};
qos_npu_nsp0: qos@27f08080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f08080 0x0 0x20>;
};
qos_npu_nsp1: qos@27f08100 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f08100 0x0 0x20>;
};
qos_emmc: qos@27f09000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f09000 0x0 0x20>;
};
qos_fspi0: qos@27f09080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f09080 0x0 0x20>;
};
qos_mmu0: qos@27f0a000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0a000 0x0 0x20>;
};
qos_mmu1: qos@27f0a080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0a080 0x0 0x20>;
};
qos_rkvdec: qos@27f0c000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0c000 0x0 0x20>;
};
qos_crypto: qos@27f0d000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0d000 0x0 0x20>;
};
qos_mmu2: qos@27f0e000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0e000 0x0 0x20>;
};
qos_ufshc: qos@27f0e080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0e080 0x0 0x20>;
};
qos_vepu0: qos@27f0f000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f0f000 0x0 0x20>;
};
qos_isp_mro: qos@27f10000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f10000 0x0 0x20>;
};
qos_isp_mwo: qos@27f10080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f10080 0x0 0x20>;
};
qos_vicap_m0: qos@27f10100 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f10100 0x0 0x20>;
};
qos_vpss_mro: qos@27f10180 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f10180 0x0 0x20>;
};
qos_vpss_mwo: qos@27f10200 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f10200 0x0 0x20>;
};
qos_hdcp0: qos@27f11000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f11000 0x0 0x20>;
};
qos_vop_m0: qos@27f12800 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f12800 0x0 0x20>;
};
qos_vop_m1ro: qos@27f12880 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f12880 0x0 0x20>;
};
qos_ebc: qos@27f13000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f13000 0x0 0x20>;
};
qos_rga0: qos@27f13080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f13080 0x0 0x20>;
};
qos_rga1: qos@27f13100 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f13100 0x0 0x20>;
};
qos_jpeg: qos@27f13180 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f13180 0x0 0x20>;
};
qos_vdpp: qos@27f13200 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f13200 0x0 0x20>;
};
qos_npu_m0: qos@27f20000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f20000 0x0 0x20>;
};
qos_npu_m1: qos@27f21000 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f21000 0x0 0x20>;
};
qos_npu_m0ro: qos@27f22080 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f22080 0x0 0x20>;
};
qos_npu_m1ro: qos@27f22100 {
compatible = "rockchip,rk3576-qos", "syscon";
reg = <0x0 0x27f22100 0x0 0x20>;
};
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;
clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
<&cru CLK_GMAC0_PTP_REF>;
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
power-domains = <&power RK3576_PD_SDGMAC>;
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";
rockchip,grf = <&sdgmac_grf>;
rockchip,php-grf = <&ioc_grf>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <8>;
snps,wr_osr_lmt = <4>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
gmac1: ethernet@2a230000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a230000 0x0 0x10000>;
clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>,
<&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
<&cru CLK_GMAC1_PTP_REF>;
clock-names = "stmmaceth", "clk_mac_ref",
"pclk_mac", "aclk_mac",
"ptp_ref";
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
power-domains = <&power RK3576_PD_SDGMAC>;
resets = <&cru SRST_A_GMAC1>;
reset-names = "stmmaceth";
rockchip,grf = <&sdgmac_grf>;
rockchip,php-grf = <&ioc_grf>;
snps,axi-config = <&gmac1_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac1_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <8>;
snps,wr_osr_lmt = <4>;
};
gmac1_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac1_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
sata0: sata@2a240000 {
compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
reg = <0x0 0x2a240000 0x0 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
<&cru CLK_RXOOB0>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_SUBPHP>;
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
sata1: sata@2a250000 {
compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
reg = <0x0 0x2a250000 0x0 0x1000>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
<&cru CLK_RXOOB1>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_SUBPHP>;
phys = <&combphy1_psu PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
ufshc: ufshc@2a2d0000 {
compatible = "rockchip,rk3576-ufshc";
reg = <0x0 0x2a2d0000 0x0 0x10000>,
<0x0 0x2b040000 0x0 0x10000>,
<0x0 0x2601f000 0x0 0x1000>,
<0x0 0x2603c000 0x0 0x1000>,
<0x0 0x2a2e0000 0x0 0x10000>;
reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
<&cru CLK_REF_UFS_CLKOUT>;
clock-names = "core", "pclk", "pclk_mphy", "ref_out";
assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&power RK3576_PD_USB>;
pinctrl-0 = <&ufs_refclk>;
pinctrl-names = "default";
resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
<&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
reset-names = "biu", "sys", "ufs", "grf";
reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
status = "disabled";
};
sfc1: spi@2a300000 {
compatible = "rockchip,sfc";
reg = <0x0 0x2a300000 0x0 0x4000>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
clock-names = "clk_sfc", "hclk_sfc";
power-domains = <&power RK3576_PD_SDGMAC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sdmmc: mmc@2a310000 {
compatible = "rockchip,rk3576-dw-mshc";
reg = <0x0 0x2a310000 0x0 0x4000>;
clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <200000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
power-domains = <&power RK3576_PD_SDGMAC>;
resets = <&cru SRST_H_SDMMC0>;
reset-names = "reset";
status = "disabled";
};
sdio: mmc@2a320000 {
compatible = "rockchip,rk3576-dw-mshc";
reg = <0x0 0x2a320000 0x0 0x4000>;
clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <200000000>;
pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>;
pinctrl-names = "default";
power-domains = <&power RK3576_PD_SDGMAC>;
resets = <&cru SRST_H_SDIO>;
reset-names = "reset";
status = "disabled";
};
sdhci: mmc@2a330000 {
compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
reg = <0x0 0x2a330000 0x0 0x10000>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
assigned-clock-rates = <200000000>, <24000000>, <200000000>;
clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
<&cru TCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <200000000>;
pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
<&emmc_cmd>, <&emmc_strb>;
pinctrl-names = "default";
power-domains = <&power RK3576_PD_NVM>;
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
<&cru SRST_T_EMMC>;
reset-names = "core", "bus", "axi", "block", "timer";
supports-cqe;
status = "disabled";
};
sfc0: spi@2a340000 {
compatible = "rockchip,sfc";
reg = <0x0 0x2a340000 0x0 0x4000>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
clock-names = "clk_sfc", "hclk_sfc";
power-domains = <&power RK3576_PD_NVM>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rng: rng@2a410000 {
compatible = "rockchip,rk3576-rng";
reg = <0x0 0x2a410000 0x0 0x200>;
clocks = <&cru HCLK_TRNG_NS>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_H_TRNG_NS>;
};
otp: otp@2a580000 {
compatible = "rockchip,rk3576-otp";
reg = <0x0 0x2a580000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
<&cru CLK_OTP_PHY_G>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
reset-names = "otp", "apb";
/* Data cells */
cpu_code: cpu-code@2 {
reg = <0x02 0x2>;
};
otp_cpu_version: cpu-version@5 {
reg = <0x05 0x1>;
bits = <3 3>;
};
otp_id: id@a {
reg = <0x0a 0x10>;
};
cpub_leakage: cpub-leakage@1e {
reg = <0x1e 0x1>;
};
cpul_leakage: cpul-leakage@1f {
reg = <0x1f 0x1>;
};
npu_leakage: npu-leakage@20 {
reg = <0x20 0x1>;
};
gpu_leakage: gpu-leakage@21 {
reg = <0x21 0x1>;
};
log_leakage: log-leakage@22 {
reg = <0x22 0x1>;
};
bigcore_tsadc_trim: bigcore-tsadc-trim@24 {
reg = <0x24 0x2>;
bits = <0 10>;
};
litcore_tsadc_trim: litcore-tsadc-trim@26 {
reg = <0x26 0x2>;
bits = <0 10>;
};
ddr_tsadc_trim: ddr-tsadc-trim@28 {
reg = <0x28 0x2>;
bits = <0 10>;
};
npu_tsadc_trim: npu-tsadc-trim@2a {
reg = <0x2a 0x2>;
bits = <0 10>;
};
gpu_tsadc_trim: gpu-tsadc-trim@2c {
reg = <0x2c 0x2>;
bits = <0 10>;
};
soc_tsadc_trim: soc-tsadc-trim@64 {
reg = <0x64 0x2>;
bits = <0 10>;
};
};
sai0: sai@2a600000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x2a600000 0x0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac0 0>, <&dmac0 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3576_PD_AUDIO>;
resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
reset-names = "m", "h";
pinctrl-names = "default";
pinctrl-0 = <&sai0m0_lrck
&sai0m0_sclk
&sai0m0_sdi0
&sai0m0_sdi1
&sai0m0_sdi2
&sai0m0_sdi3
&sai0m0_sdo0
&sai0m0_sdo1
&sai0m0_sdo2
&sai0m0_sdo3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI0";
status = "disabled";
};
sai1: sai@2a610000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x2a610000 0x0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac0 2>, <&dmac0 3>;
dma-names = "tx", "rx";
power-domains = <&power RK3576_PD_AUDIO>;
resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
reset-names = "m", "h";
pinctrl-names = "default";
pinctrl-0 = <&sai1m0_lrck
&sai1m0_sclk
&sai1m0_sdi0
&sai1m0_sdo0
&sai1m0_sdo1
&sai1m0_sdo2
&sai1m0_sdo3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI1";
status = "disabled";
};
sai2: sai@2a620000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x2a620000 0x0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac1 0>, <&dmac1 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3576_PD_AUDIO>;
resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
reset-names = "m", "h";
pinctrl-names = "default";
pinctrl-0 = <&sai2m0_lrck
&sai2m0_sclk
&sai2m0_sdi
&sai2m0_sdo>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI2";
status = "disabled";
};
sai3: sai@2a630000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x2a630000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac1 2>, <&dmac1 3>;
dma-names = "tx", "rx";
power-domains = <&power RK3576_PD_AUDIO>;
resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
reset-names = "m", "h";
pinctrl-names = "default";
pinctrl-0 = <&sai3m0_lrck
&sai3m0_sclk
&sai3m0_sdi
&sai3m0_sdo>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI3";
status = "disabled";
};
sai4: sai@2a640000 {
compatible = "rockchip,rk3576-sai";
reg = <0x0 0x2a640000 0x0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
clock-names = "mclk", "hclk";
dmas = <&dmac2 0>, <&dmac2 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3576_PD_AUDIO>;
resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
reset-names = "m", "h";
pinctrl-names = "default";
pinctrl-0 = <&sai4m0_lrck
&sai4m0_sclk
&sai4m0_sdi
&sai4m0_sdo>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI4";
status = "disabled";
};
gic: interrupt-controller@2a701000 {
compatible = "arm,gic-400";
reg = <0x0 0x2a701000 0 0x10000>,
<0x0 0x2a702000 0 0x10000>,
<0x0 0x2a704000 0 0x10000>,
<0x0 0x2a706000 0 0x10000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
};
dmac0: dma-controller@2ab90000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x2ab90000 0x0 0x4000>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC0>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
};
dmac1: dma-controller@2abb0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x2abb0000 0x0 0x4000>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
};
dmac2: dma-controller@2abd0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x2abd0000 0x0 0x4000>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
};
i2c1: i2c@2ac40000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac40000 0x0 0x1000>;
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@2ac50000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac50000 0x0 0x1000>;
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@2ac60000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac60000 0x0 0x1000>;
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@2ac70000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac70000 0x0 0x1000>;
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@2ac80000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac80000 0x0 0x1000>;
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@2ac90000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ac90000 0x0 0x1000>;
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@2aca0000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2aca0000 0x0 0x1000>;
clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@2acb0000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2acb0000 0x0 0x1000>;
clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
timer0: timer@2acc0000 {
compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
reg = <0x0 0x2acc0000 0x0 0x20>;
clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>;
clock-names = "pclk", "timer";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
};
wdt: watchdog@2ace0000 {
compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
reg = <0x0 0x2ace0000 0x0 0x100>;
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
spi0: spi@2acf0000 {
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
reg = <0x0 0x2acf0000 0x0 0x1000>;
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 14>, <&dmac0 15>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@2ad00000 {
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
reg = <0x0 0x2ad00000 0x0 0x1000>;
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 16>, <&dmac0 17>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@2ad10000 {
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
reg = <0x0 0x2ad10000 0x0 0x1000>;
clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac1 15>, <&dmac1 16>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@2ad20000 {
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
reg = <0x0 0x2ad20000 0x0 0x1000>;
clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac1 17>, <&dmac1 18>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@2ad30000 {
compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
reg = <0x0 0x2ad30000 0x0 0x1000>;
clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac2 12>, <&dmac2 13>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@2ad40000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ad40000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 6>, <&dmac0 7>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart0m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart2: serial@2ad50000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ad50000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 10>, <&dmac0 11>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
};
uart3: serial@2ad60000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ad60000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 12>, <&dmac0 13>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart3m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart4: serial@2ad70000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ad70000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac1 9>, <&dmac1 10>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart4m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart5: serial@2ad80000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ad80000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac1 11>, <&dmac1 12>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart5m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart6: serial@2ad90000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ad90000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac1 13>, <&dmac1 14>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart6m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart7: serial@2ada0000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2ada0000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac2 6>, <&dmac2 7>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart7m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart8: serial@2adb0000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2adb0000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac2 8>, <&dmac2 9>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart8m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
uart9: serial@2adc0000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2adc0000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac2 10>, <&dmac2 11>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&uart9m0_xfer>;
pinctrl-names = "default";
status = "disabled";
};
saradc: adc@2ae00000 {
compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
reg = <0x0 0x2ae00000 0x0 0x10000>;
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
#io-channel-cells = <1>;
status = "disabled";
};
tsadc: tsadc@2ae70000 {
compatible = "rockchip,rk3576-tsadc";
reg = <0x0 0x2ae70000 0x0 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru CLK_TSADC>;
assigned-clock-rates = <2000000>;
resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
reset-names = "tsadc-apb", "tsadc";
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
#address-cells = <1>;
#size-cells = <0>;
sensor@0 {
reg = <0>;
nvmem-cells = <&soc_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@1 {
reg = <1>;
nvmem-cells = <&bigcore_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@2 {
reg = <2>;
nvmem-cells = <&litcore_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@3 {
reg = <3>;
nvmem-cells = <&ddr_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@4 {
reg = <4>;
nvmem-cells = <&npu_tsadc_trim>;
nvmem-cell-names = "trim";
};
sensor@5 {
reg = <5>;
nvmem-cells = <&gpu_tsadc_trim>;
nvmem-cell-names = "trim";
};
};
i2c9: i2c@2ae80000 {
compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0x2ae80000 0x0 0x1000>;
clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2c9m0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart10: serial@2afc0000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2afc0000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac2 21>, <&dmac2 22>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart10m0_xfer>;
status = "disabled";
};
uart11: serial@2afd0000 {
compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
reg = <0x0 0x2afd0000 0x0 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac2 23>, <&dmac2 24>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart11m0_xfer>;
status = "disabled";
};
mipidcphy: phy@2b020000 {
compatible = "rockchip,rk3576-mipi-dcphy";
reg = <0x0 0x2b020000 0x0 0x10000>;
clocks = <&cru PCLK_MIPI_DCPHY>,
<&cru CLK_PHY_REF_SRC>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY>,
<&cru SRST_P_MIPI_DCPHY>,
<&cru SRST_P_DCPHY_GRF>,
<&cru SRST_S_MIPI_DCPHY>;
reset-names = "m_phy", "apb", "grf", "s_phy";
rockchip,grf = <&mipidcphy_grf>;
#phy-cells = <1>;
status = "disabled";
};
combphy0_ps: phy@2b050000 {
compatible = "rockchip,rk3576-naneng-combphy";
reg = <0x0 0x2b050000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PCIE0_PHY>,
<&cru PCLK_PCIE2_COMBOPHY0>,
<&cru PCLK_PCIE0>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PCIE0_PIPE_PHY>,
<&cru SRST_P_PCIE2_COMBOPHY0>;
reset-names = "phy", "apb";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
status = "disabled";
};
combphy1_psu: phy@2b060000 {
compatible = "rockchip,rk3576-naneng-combphy";
reg = <0x0 0x2b060000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PCIE1_PHY>,
<&cru PCLK_PCIE2_COMBOPHY1>,
<&cru PCLK_PCIE1>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PCIE1_PIPE_PHY>,
<&cru SRST_P_PCIE2_COMBOPHY1>;
reset-names = "phy", "apb";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
status = "disabled";
};
usbdp_phy: phy@2b010000 {
compatible = "rockchip,rk3576-usbdp-phy";
reg = <0x0 0x2b010000 0x0 0x10000>;
#phy-cells = <1>;
clocks = <&cru CLK_PHY_REF_SRC >,
<&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
<&cru PCLK_USBDPPHY>,
<&u2phy0>;
clock-names = "refclk", "immortal", "pclk", "utmi";
resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
<&cru SRST_USBDP_COMBO_PHY_CMN>,
<&cru SRST_USBDP_COMBO_PHY_LANE>,
<&cru SRST_USBDP_COMBO_PHY_PCS>,
<&cru SRST_P_USBDPPHY>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
rockchip,u2phy-grf = <&usb2phy_grf>;
rockchip,usb-grf = <&usb_grf>;
rockchip,usbdpphy-grf = <&usbdpphy_grf>;
rockchip,vo-grf = <&vo1_grf>;
status = "disabled";
};
hdptxphy: hdmiphy@2b000000 {
compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
reg = <0x0 0x2b000000 0x0 0x2000>;
clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
clock-names = "ref", "apb";
#clock-cells = <0>;
resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
<&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
reset-names = "apb", "init", "cmn", "lane";
rockchip,grf = <&hdptxphy_grf>;
#phy-cells = <0>;
status = "disabled";
};
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;
ranges = <0x0 0x0 0x3ff88000 0x78000>;
#address-cells = <1>;
#size-cells = <1>;
/* start address and size should be 4k align */
rkvdec_sram: rkvdec-sram@0 {
reg = <0x0 0x78000>;
};
};
scmi_shmem: scmi-shmem@4010f000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x4010f000 0x0 0x100>;
};
};
};
#include "rk3576-pinctrl.dtsi"
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