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ec4daace64
The gpio0_mipi_csi DT nodes are enabled by default, but they are
dependent on the irqsteer_csi nodes, which are not enabled. This causes
the gpio0_mipi_csi GPIOs to be probe deferred. Since these GPIOs can be
used independently of the CSI controller, enable irqsteer_csi by default
too to prevent them from being deferred and to ensure they work out of
the box.
Fixes: 2217f82437 ("arm64: dts: imx8: add capture controller for i.MX8's img subsystem")
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
427 lines
12 KiB
Plaintext
427 lines
12 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019-2021 NXP
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* Zhou Guoniu <guoniu.zhou@nxp.com>
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*/
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img_ipg_clk: clock-img-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "img_ipg_clk";
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};
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img_pxl_clk: clock-img-pxl {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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clock-output-names = "img_pxl_clk";
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};
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img_subsys: bus@58000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x58000000 0x0 0x58000000 0x1000000>;
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isi: isi@58100000 {
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reg = <0x58100000 0x80000>;
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interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
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<&pdma1_lpcg IMX_LPCG_CLK_0>,
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<&pdma2_lpcg IMX_LPCG_CLK_0>,
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<&pdma3_lpcg IMX_LPCG_CLK_0>,
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<&pdma4_lpcg IMX_LPCG_CLK_0>,
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<&pdma5_lpcg IMX_LPCG_CLK_0>,
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<&pdma6_lpcg IMX_LPCG_CLK_0>,
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<&pdma7_lpcg IMX_LPCG_CLK_0>;
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clock-names = "per0", "per1", "per2", "per3",
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"per4", "per5", "per6", "per7";
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interrupt-parent = <&gic>;
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power-domains = <&pd IMX_SC_R_ISI_CH0>,
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<&pd IMX_SC_R_ISI_CH1>,
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<&pd IMX_SC_R_ISI_CH2>,
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<&pd IMX_SC_R_ISI_CH3>,
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<&pd IMX_SC_R_ISI_CH4>,
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<&pd IMX_SC_R_ISI_CH5>,
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<&pd IMX_SC_R_ISI_CH6>,
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<&pd IMX_SC_R_ISI_CH7>;
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status = "disabled";
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};
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irqsteer_csi0: irqsteer@58220000 {
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compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
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reg = <0x58220000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_ipg_clk>;
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clock-names = "ipg";
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interrupt-parent = <&gic>;
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power-domains = <&pd IMX_SC_R_CSI_0>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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};
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gpio0_mipi_csi0: gpio@58222000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x58222000 0x1000>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts = <0>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-parent = <&irqsteer_csi0>;
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power-domains = <&pd IMX_SC_R_CSI_0>;
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};
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csi0_core_lpcg: clock-controller@58223018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58223018 0x4>;
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clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "csi0_lpcg_core_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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csi0_esc_lpcg: clock-controller@5822301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5822301c 0x4>;
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clocks = <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "csi0_lpcg_esc_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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i2c_mipi_csi0: i2c@58226000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x58226000 0x1000>;
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interrupts = <8>;
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clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>,
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<&img_ipg_clk>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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interrupt-parent = <&irqsteer_csi0>;
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power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
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status = "disabled";
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};
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mipi_csi_0: csi@58227000 {
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compatible = "fsl,imx8qxp-mipi-csi2";
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reg = <0x58227000 0x1000>,
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<0x58221000 0x1000>;
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clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
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<&csi0_esc_lpcg IMX_LPCG_CLK_4>,
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<&csi0_pxl_lpcg IMX_LPCG_CLK_0>;
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clock-names = "core", "esc", "ui";
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assigned-clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
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<&csi0_esc_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-rates = <360000000>, <72000000>;
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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resets = <&scu_reset IMX_SC_R_CSI_0>;
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status = "disabled";
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};
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irqsteer_csi1: irqsteer@58240000 {
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compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
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reg = <0x58240000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_ipg_clk>;
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clock-names = "ipg";
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interrupt-parent = <&gic>;
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power-domains = <&pd IMX_SC_R_CSI_1>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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};
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gpio0_mipi_csi1: gpio@58242000 {
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compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
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reg = <0x58242000 0x1000>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts = <0>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-parent = <&irqsteer_csi1>;
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power-domains = <&pd IMX_SC_R_CSI_1>;
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};
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csi1_core_lpcg: clock-controller@58243018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58243018 0x4>;
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clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "csi1_lpcg_core_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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csi1_esc_lpcg: clock-controller@5824301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5824301c 0x4>;
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clocks = <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "csi1_lpcg_esc_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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i2c_mipi_csi1: i2c@58246000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x58246000 0x1000>;
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interrupts = <8>;
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clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>,
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<&img_ipg_clk>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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interrupt-parent = <&irqsteer_csi1>;
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power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
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status = "disabled";
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};
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mipi_csi_1: csi@58247000 {
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compatible = "fsl,imx8qxp-mipi-csi2";
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reg = <0x58247000 0x1000>,
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<0x58241000 0x1000>;
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clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
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<&csi1_esc_lpcg IMX_LPCG_CLK_4>,
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<&csi1_pxl_lpcg IMX_LPCG_CLK_0>;
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clock-names = "core", "esc", "ui";
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assigned-clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
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<&csi1_esc_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-rates = <360000000>, <72000000>;
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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resets = <&scu_reset IMX_SC_R_CSI_1>;
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status = "disabled";
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};
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irqsteer_parallel: irqsteer@58260000 {
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compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
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reg = <0x58260000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_dummy>;
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clock-names = "ipg";
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interrupt-parent = <&gic>;
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power-domains = <&pd IMX_SC_R_PI_0>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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status = "disabled";
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};
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pi0_ipg_lpcg: clock-controller@58263004 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58263004 0x4>;
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clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "pi0_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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pi0_pxl_lpcg: clock-controller@58263018 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58263018 0x4>;
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clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pi0_lpcg_pxl_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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pi0_misc_lpcg: clock-controller@5826301c {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5826301c 0x4>;
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clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pi0_lpcg_misc_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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i2c0_parallel: i2c@58266000 {
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x58266000 0x1000>;
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interrupts = <8>;
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clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>,
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<&img_ipg_clk>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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interrupt-parent = <&irqsteer_parallel>;
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power-domains = <&pd IMX_SC_R_PI_0_I2C_0>;
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status = "disabled";
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};
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jpegdec: jpegdec@58400000 {
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reg = <0x58400000 0x00050000>;
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interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
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assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-rates = <200000000>, <200000000>;
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power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
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<&pd IMX_SC_R_MJPEG_DEC_S0>;
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};
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jpegenc: jpegenc@58450000 {
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reg = <0x58450000 0x00050000>;
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interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
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assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
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<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
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assigned-clock-rates = <200000000>, <200000000>;
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power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
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<&pd IMX_SC_R_MJPEG_ENC_S0>;
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};
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pdma0_lpcg: clock-controller@58500000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58500000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma0_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH0>;
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};
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pdma1_lpcg: clock-controller@58510000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58510000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma1_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH1>;
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};
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pdma2_lpcg: clock-controller@58520000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58520000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma2_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH2>;
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};
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pdma3_lpcg: clock-controller@58530000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58530000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma3_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH3>;
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};
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pdma4_lpcg: clock-controller@58540000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58540000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma4_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH4>;
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};
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pdma5_lpcg: clock-controller@58550000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58550000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma5_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH5>;
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};
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pdma6_lpcg: clock-controller@58560000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58560000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma6_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH6>;
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};
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pdma7_lpcg: clock-controller@58570000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58570000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "pdma7_lpcg_clk";
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power-domains = <&pd IMX_SC_R_ISI_CH7>;
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};
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csi0_pxl_lpcg: clock-controller@58580000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x58580000 0x10000>;
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clocks = <&img_pxl_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>;
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clock-output-names = "csi0_lpcg_pxl_clk";
|
|
power-domains = <&pd IMX_SC_R_CSI_0>;
|
|
};
|
|
|
|
csi1_pxl_lpcg: clock-controller@58590000 {
|
|
compatible = "fsl,imx8qxp-lpcg";
|
|
reg = <0x58590000 0x10000>;
|
|
clocks = <&img_pxl_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <IMX_LPCG_CLK_0>;
|
|
clock-output-names = "csi1_lpcg_pxl_clk";
|
|
power-domains = <&pd IMX_SC_R_CSI_1>;
|
|
};
|
|
|
|
hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 {
|
|
compatible = "fsl,imx8qxp-lpcg";
|
|
reg = <0x585a0000 0x10000>;
|
|
clocks = <&img_pxl_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <IMX_LPCG_CLK_0>;
|
|
clock-output-names = "hdmi_rx_lpcg_pxl_link_clk";
|
|
power-domains = <&pd IMX_SC_R_HDMI_RX>;
|
|
};
|
|
|
|
img_jpeg_dec_lpcg: clock-controller@585d0000 {
|
|
compatible = "fsl,imx8qxp-lpcg";
|
|
reg = <0x585d0000 0x10000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&img_ipg_clk>, <&img_ipg_clk>;
|
|
clock-indices = <IMX_LPCG_CLK_0>,
|
|
<IMX_LPCG_CLK_4>;
|
|
clock-output-names = "img_jpeg_dec_lpcg_clk",
|
|
"img_jpeg_dec_lpcg_ipg_clk";
|
|
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
|
|
};
|
|
|
|
img_jpeg_enc_lpcg: clock-controller@585f0000 {
|
|
compatible = "fsl,imx8qxp-lpcg";
|
|
reg = <0x585f0000 0x10000>;
|
|
#clock-cells = <1>;
|
|
clocks = <&img_ipg_clk>, <&img_ipg_clk>;
|
|
clock-indices = <IMX_LPCG_CLK_0>,
|
|
<IMX_LPCG_CLK_4>;
|
|
clock-output-names = "img_jpeg_enc_lpcg_clk",
|
|
"img_jpeg_enc_lpcg_ipg_clk";
|
|
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
|
|
};
|
|
};
|