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Add mt8189 audio afe document. Signed-off-by: Cyril Chao <Cyril.Chao@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251031073216.8662-8-Cyril.Chao@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
179 lines
6.2 KiB
YAML
179 lines
6.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mediatek,mt8189-afe-pcm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Audio Front End PCM controller for MT8189
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maintainers:
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- Darren Ye <darren.ye@mediatek.com>
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- Cyril Chao <cyril.chao@mediatek.com>
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properties:
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compatible:
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const: mediatek,mt8189-afe-pcm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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memory-region:
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maxItems: 1
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mediatek,apmixedsys:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: To set up the apll12 tuner
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: mux for audio intbus
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- description: mux for audio engen1
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- description: mux for audio engen2
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- description: mux for audio h
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- description: audio apll1 clock
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- description: audio apll2 clock
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- description: audio apll1 divide4
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- description: audio apll2 divide4
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- description: audio apll12 divide for i2sin0
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- description: audio apll12 divide for i2sin1
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- description: audio apll12 divide for i2sout0
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- description: audio apll12 divide for i2sout1
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- description: audio apll12 divide for fmi2s
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- description: audio apll12 divide for tdmout mck
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- description: audio apll12 divide for tdmout bck
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- description: mux for audio apll1
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- description: mux for audio apll2
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- description: mux for i2sin0 mck
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- description: mux for i2sin1 mck
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- description: mux for i2sout0 mck
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- description: mux for i2sout1 mck
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- description: mux for fmi2s mck
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- description: mux for tdmout mck
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- description: 26m clock
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- description: audio slv clock
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- description: audio mst clock
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- description: audio intbus clock
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clock-names:
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items:
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- const: top_aud_intbus
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- const: top_aud_eng1
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- const: top_aud_eng2
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- const: top_aud_h
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- const: apll1
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- const: apll2
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- const: apll1_d4
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- const: apll2_d4
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- const: apll12_div_i2sin0
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- const: apll12_div_i2sin1
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- const: apll12_div_i2sout0
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- const: apll12_div_i2sout1
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- const: apll12_div_fmi2s
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- const: apll12_div_tdmout_m
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- const: apll12_div_tdmout_b
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- const: top_apll1
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- const: top_apll2
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- const: top_i2sin0
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- const: top_i2sin1
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- const: top_i2sout0
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- const: top_i2sout1
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- const: top_fmi2s
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- const: top_dptx
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- const: clk26m
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- const: aud_slv_ck_peri
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- const: aud_mst_ck_peri
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- const: aud_intbus_ck_peri
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required:
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- compatible
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- reg
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- interrupts
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- memory-region
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- power-domains
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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afe@11050000 {
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compatible = "mediatek,mt8189-afe-pcm";
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reg = <0 0x11050000 0 0x10000>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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memory-region = <&afe_dma_mem_reserved>;
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pinctrl-names = "default";
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pinctrl-0 = <&aud_pins_default>;
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power-domains = <&scpsys 1>; //MT8189_POWER_DOMAIN_AUDIO
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clocks = <&topckgen_clk 23>, //CLK_TOP_AUD_INTBUS_SEL
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<&topckgen_clk 39>, //CLK_TOP_AUD_ENGEN1_SEL
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<&topckgen_clk 40>, //CLK_TOP_AUD_ENGEN2_SEL
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<&topckgen_clk 49>, //CLK_TOP_AUDIO_H_SEL
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<&topckgen_clk 146>, //CLK_TOP_APLL1
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<&topckgen_clk 151>, //CLK_TOP_APLL2
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<&topckgen_clk 148>, //CLK_TOP_APLL1_D4
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<&topckgen_clk 153>, //CLK_TOP_APLL2_D4
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<&topckgen_clk 93>, //CLK_TOP_APLL12_CK_DIV_I2SIN0
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<&topckgen_clk 94>, //CLK_TOP_APLL12_CK_DIV_I2SIN1
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<&topckgen_clk 95>, //CLK_TOP_APLL12_CK_DIV_I2SOUT0
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<&topckgen_clk 96>, //CLK_TOP_APLL12_CK_DIV_I2SOUT1
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<&topckgen_clk 97>, //CLK_TOP_APLL12_CK_DIV_FMI2S
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<&topckgen_clk 98>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M
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<&topckgen_clk 99>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_B
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<&topckgen_clk 44>, //CLK_TOP_AUD_1_SEL
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<&topckgen_clk 45>, //CLK_TOP_AUD_2_SEL
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<&topckgen_clk 78>, //CLK_TOP_APLL_I2SIN0_MCK_SEL
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<&topckgen_clk 79>, //CLK_TOP_APLL_I2SIN1_MCK_SEL
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<&topckgen_clk 84>, //CLK_TOP_APLL_I2SOUT0_MCK_SEL
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<&topckgen_clk 85>, //CLK_TOP_APLL_I2SOUT1_MCK_SEL
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<&topckgen_clk 90>, //CLK_TOP_APLL_FMI2S_MCK_SEL
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<&topckgen_clk 91>, //CLK_TOP_APLL_TDMOUT_MCK_SEL
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<&topckgen_clk 191>, //CLK_TOP_TCK_26M_MX9
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<&pericfg_ao_clk 77>, //CLK_PERAO_AUDIO0
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<&pericfg_ao_clk 78>, //CLK_PERAO_AUDIO1
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<&pericfg_ao_clk 79>; //CLK_PERAO_AUDIO2
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clock-names = "top_aud_intbus",
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"top_aud_eng1",
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"top_aud_eng2",
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"top_aud_h",
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"apll1",
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"apll2",
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"apll1_d4",
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"apll2_d4",
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"apll12_div_i2sin0",
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"apll12_div_i2sin1",
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"apll12_div_i2sout0",
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"apll12_div_i2sout1",
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"apll12_div_fmi2s",
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"apll12_div_tdmout_m",
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"apll12_div_tdmout_b",
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"top_apll1",
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"top_apll2",
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"top_i2sin0",
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"top_i2sin1",
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"top_i2sout0",
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"top_i2sout1",
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"top_fmi2s",
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"top_dptx",
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"clk26m",
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"aud_slv_ck_peri",
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"aud_mst_ck_peri",
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"aud_intbus_ck_peri";
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};
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};
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...
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