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e1bb4b36a7
Extend the Lantiq GSWIP device tree binding to also cover MaxLinear GSW1xx switches which are based on the same hardware IP but connected via MDIO instead of being memory-mapped. Add compatible strings for MaxLinear GSW120, GSW125, GSW140, GSW141, and GSW145 switches and adjust the schema to handle the different connection methods with conditional properties. Add MaxLinear GSW125 example showing MDIO-connected configuration. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/fc96f1dedb2b418a63e69960356dde7f6eb86424.1762170107.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
351 lines
9.3 KiB
YAML
351 lines
9.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lantiq GSWIP and MaxLinear GSW1xx Ethernet switches
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description:
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Lantiq GSWIP and MaxLinear GSW1xx switches share the same hardware IP.
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Lantiq switches are embedded in SoCs and accessed via memory-mapped I/O,
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while MaxLinear switches are standalone ICs connected via MDIO.
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$ref: dsa.yaml#
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maintainers:
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- Hauke Mehrtens <hauke@hauke-m.de>
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properties:
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compatible:
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enum:
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- lantiq,xrx200-gswip
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- lantiq,xrx300-gswip
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- lantiq,xrx330-gswip
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- maxlinear,gsw120
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- maxlinear,gsw125
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- maxlinear,gsw140
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- maxlinear,gsw141
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- maxlinear,gsw145
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reg:
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minItems: 1
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maxItems: 3
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reg-names:
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items:
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- const: switch
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- const: mdio
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- const: mii
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mdio:
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$ref: /schemas/net/mdio.yaml#
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unevaluatedProperties: false
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properties:
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compatible:
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const: lantiq,xrx200-mdio
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gphy-fw:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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compatible:
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items:
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- enum:
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- lantiq,xrx200-gphy-fw
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- lantiq,xrx300-gphy-fw
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- lantiq,xrx330-gphy-fw
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- const: lantiq,gphy-fw
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lantiq,rcu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the RCU syscon
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patternProperties:
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"^gphy@[0-9a-f]{1,2}$":
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type: object
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additionalProperties: false
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properties:
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reg:
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minimum: 0
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maximum: 255
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description:
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Offset of the GPHY firmware register in the RCU register range
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resets:
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items:
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- description: GPHY reset line
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reset-names:
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items:
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- const: gphy
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required:
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- reg
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required:
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- compatible
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- lantiq,rcu
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additionalProperties: false
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patternProperties:
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"^(ethernet-)?ports$":
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type: object
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patternProperties:
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"^(ethernet-)?port@[0-6]$":
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$ref: dsa-port.yaml#
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unevaluatedProperties: false
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properties:
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maxlinear,rmii-refclk-out:
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type: boolean
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description:
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Configure the RMII reference clock to be a clock output
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rather than an input. Only applicable for RMII mode.
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tx-internal-delay-ps:
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enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
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description:
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RGMII TX Clock Delay defined in pico seconds.
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The delay lines adjust the MII clock vs. data timing.
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If this property is not present the delay is determined by
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the interface mode.
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rx-internal-delay-ps:
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enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500]
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description:
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RGMII RX Clock Delay defined in pico seconds.
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The delay lines adjust the MII clock vs. data timing.
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If this property is not present the delay is determined by
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the interface mode.
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required:
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- compatible
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- lantiq,xrx200-gswip
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- lantiq,xrx300-gswip
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- lantiq,xrx330-gswip
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then:
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properties:
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reg:
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minItems: 3
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maxItems: 3
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mdio:
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required:
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- compatible
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else:
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properties:
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reg:
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maxItems: 1
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reg-names: false
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gphy-fw: false
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unevaluatedProperties: false
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examples:
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- |
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switch@e108000 {
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compatible = "lantiq,xrx200-gswip";
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reg = <0xe108000 0x3100>, /* switch */
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<0xe10b100 0xd8>, /* mdio */
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<0xe10b1d8 0x130>; /* mii */
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dsa,member = <0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan3";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2000>;
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};
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy11>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy13>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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port@6 {
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reg = <0x6>;
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phy-mode = "internal";
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ethernet = <ð0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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phy11: ethernet-phy@11 {
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reg = <0x11>;
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};
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phy13: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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gphy-fw {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
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lantiq,rcu = <&rcu0>;
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gphy@20 {
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reg = <0x20>;
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resets = <&reset0 31 30>;
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reset-names = "gphy";
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};
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gphy@68 {
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reg = <0x68>;
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resets = <&reset0 29 28>;
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reset-names = "gphy";
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};
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};
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};
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- |
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#include <dt-bindings/leds/common.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "maxlinear,gsw125";
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reg = <0x1f>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-handle = <&switchphy0>;
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phy-mode = "internal";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&switchphy1>;
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phy-mode = "internal";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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phy-mode = "1000base-x";
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managed = "in-band-status";
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};
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port@5 {
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reg = <5>;
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phy-mode = "rgmii-id";
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tx-internal-delay-ps = <2000>;
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rx-internal-delay-ps = <2000>;
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ethernet = <ð0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switchphy0: switchphy@0 {
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reg = <0>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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};
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};
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};
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switchphy1: switchphy@1 {
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reg = <1>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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};
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};
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};
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};
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};
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};
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