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The CAN cores on Polarfire SoC both have a reset. The platform firmware
brings both cores out of reset, but the linux driver must use them
during normal operation. The resets should have been made required, but
this is one of the things that can happen when the binding is written
without driver support.
Fixes: c878d518d7 ("dt-bindings: can: mpfs: document the mpfs CAN controller")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20251121-sample-footsore-743d81772efc@spud
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
57 lines
1.0 KiB
YAML
57 lines
1.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title:
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Microchip PolarFire SoC (MPFS) can controller
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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allOf:
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- $ref: can-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- const: microchip,pic64gx-can
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- const: microchip,mpfs-can
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- const: microchip,mpfs-can
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: AHB peripheral clock
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- description: CAN bus clock
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- resets
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additionalProperties: false
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examples:
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- |
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can@2010c000 {
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compatible = "microchip,mpfs-can";
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reg = <0x2010c000 0x1000>;
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clocks = <&clkcfg 17>, <&clkcfg 37>;
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resets = <&clkcfg 17>;
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interrupt-parent = <&plic>;
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interrupts = <56>;
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};
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