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The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Link: https://lkml.kernel.org/r/20251113072806.795029-4-zhangchunyan@iscas.ac.cn Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Axel Rasmussen <axelrasmussen@google.com> Cc: Christian Brauner <brauner@kernel.org> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Conor Dooley <conor@kernel.org> Cc: David Hildenbrand <david@redhat.com> Cc: Jan Kara <jack@suse.cz> Cc: Liam Howlett <liam.howlett@oracle.com> Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Cc: Michal Hocko <mhocko@suse.com> Cc: Mike Rapoport <rppt@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Peter Xu <peterx@redhat.com> Cc: Rob Herring <robh@kernel.org> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Yuanchu Xie <yuanchu@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copied from arch/arm64/include/asm/hwcap.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_HWCAP_H
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#define _ASM_RISCV_HWCAP_H
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#include <uapi/asm/hwcap.h>
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#define RISCV_ISA_EXT_a ('a' - 'a')
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#define RISCV_ISA_EXT_c ('c' - 'a')
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#define RISCV_ISA_EXT_d ('d' - 'a')
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#define RISCV_ISA_EXT_f ('f' - 'a')
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#define RISCV_ISA_EXT_h ('h' - 'a')
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#define RISCV_ISA_EXT_i ('i' - 'a')
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#define RISCV_ISA_EXT_m ('m' - 'a')
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#define RISCV_ISA_EXT_q ('q' - 'a')
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#define RISCV_ISA_EXT_v ('v' - 'a')
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/*
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* These macros represent the logical IDs of each multi-letter RISC-V ISA
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* extension and are used in the ISA bitmap. The logical IDs start from
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* RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
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* letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
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* to allocate the bitmap and may be increased when necessary.
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*
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* New extensions should just be added to the bottom, rather than added
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* alphabetically, in order to avoid unnecessary shuffling.
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*/
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#define RISCV_ISA_EXT_BASE 26
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#define RISCV_ISA_EXT_SSCOFPMF 26
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#define RISCV_ISA_EXT_SSTC 27
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#define RISCV_ISA_EXT_SVINVAL 28
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#define RISCV_ISA_EXT_SVPBMT 29
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#define RISCV_ISA_EXT_ZBB 30
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#define RISCV_ISA_EXT_ZICBOM 31
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#define RISCV_ISA_EXT_ZIHINTPAUSE 32
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#define RISCV_ISA_EXT_SVNAPOT 33
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#define RISCV_ISA_EXT_ZICBOZ 34
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#define RISCV_ISA_EXT_SMAIA 35
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#define RISCV_ISA_EXT_SSAIA 36
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#define RISCV_ISA_EXT_ZBA 37
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#define RISCV_ISA_EXT_ZBS 38
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#define RISCV_ISA_EXT_ZICNTR 39
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#define RISCV_ISA_EXT_ZICSR 40
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#define RISCV_ISA_EXT_ZIFENCEI 41
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#define RISCV_ISA_EXT_ZIHPM 42
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#define RISCV_ISA_EXT_SMSTATEEN 43
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#define RISCV_ISA_EXT_ZICOND 44
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#define RISCV_ISA_EXT_ZBC 45
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#define RISCV_ISA_EXT_ZBKB 46
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#define RISCV_ISA_EXT_ZBKC 47
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#define RISCV_ISA_EXT_ZBKX 48
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#define RISCV_ISA_EXT_ZKND 49
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#define RISCV_ISA_EXT_ZKNE 50
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#define RISCV_ISA_EXT_ZKNH 51
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#define RISCV_ISA_EXT_ZKR 52
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#define RISCV_ISA_EXT_ZKSED 53
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#define RISCV_ISA_EXT_ZKSH 54
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#define RISCV_ISA_EXT_ZKT 55
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#define RISCV_ISA_EXT_ZVBB 56
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#define RISCV_ISA_EXT_ZVBC 57
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#define RISCV_ISA_EXT_ZVKB 58
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#define RISCV_ISA_EXT_ZVKG 59
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#define RISCV_ISA_EXT_ZVKNED 60
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#define RISCV_ISA_EXT_ZVKNHA 61
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#define RISCV_ISA_EXT_ZVKNHB 62
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#define RISCV_ISA_EXT_ZVKSED 63
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#define RISCV_ISA_EXT_ZVKSH 64
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#define RISCV_ISA_EXT_ZVKT 65
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#define RISCV_ISA_EXT_ZFH 66
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#define RISCV_ISA_EXT_ZFHMIN 67
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#define RISCV_ISA_EXT_ZIHINTNTL 68
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#define RISCV_ISA_EXT_ZVFH 69
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#define RISCV_ISA_EXT_ZVFHMIN 70
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#define RISCV_ISA_EXT_ZFA 71
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#define RISCV_ISA_EXT_ZTSO 72
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#define RISCV_ISA_EXT_ZACAS 73
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#define RISCV_ISA_EXT_ZVE32X 74
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#define RISCV_ISA_EXT_ZVE32F 75
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#define RISCV_ISA_EXT_ZVE64X 76
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#define RISCV_ISA_EXT_ZVE64F 77
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#define RISCV_ISA_EXT_ZVE64D 78
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#define RISCV_ISA_EXT_ZIMOP 79
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#define RISCV_ISA_EXT_ZCA 80
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#define RISCV_ISA_EXT_ZCB 81
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#define RISCV_ISA_EXT_ZCD 82
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#define RISCV_ISA_EXT_ZCF 83
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#define RISCV_ISA_EXT_ZCMOP 84
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#define RISCV_ISA_EXT_ZAWRS 85
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#define RISCV_ISA_EXT_SVVPTC 86
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#define RISCV_ISA_EXT_SMMPM 87
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#define RISCV_ISA_EXT_SMNPM 88
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#define RISCV_ISA_EXT_SSNPM 89
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#define RISCV_ISA_EXT_ZABHA 90
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#define RISCV_ISA_EXT_ZICCRSE 91
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#define RISCV_ISA_EXT_SVADE 92
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#define RISCV_ISA_EXT_SVADU 93
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#define RISCV_ISA_EXT_ZFBFMIN 94
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#define RISCV_ISA_EXT_ZVFBFMIN 95
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#define RISCV_ISA_EXT_ZVFBFWMA 96
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#define RISCV_ISA_EXT_ZAAMO 97
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#define RISCV_ISA_EXT_ZALRSC 98
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#define RISCV_ISA_EXT_ZICBOP 99
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#define RISCV_ISA_EXT_SVRSW60T59B 100
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#define RISCV_ISA_EXT_XLINUXENVCFG 127
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#define RISCV_ISA_EXT_MAX 128
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#define RISCV_ISA_EXT_INVALID U32_MAX
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#ifdef CONFIG_RISCV_M_MODE
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#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
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#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM
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#else
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#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
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#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM
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#endif
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#endif /* _ASM_RISCV_HWCAP_H */
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