mirror of
https://github.com/torvalds/linux.git
synced 2025-12-07 20:06:24 +00:00
8e88602e99
Add device tree source describing the Tenstorrent Blackhole SoC and the Blackhole P100 and P150 PCIe cards. There are no differences between the P100 and P150 cards from the perspective of an OS kernel like Linux running on the X280 cores. There is a virtual UART implemented in OpenSBI firmware that allows a console program on the PCIe host to communicate through shared memory with Linux running on the Blackhole card. CONFIG_HVC_RISCV_SBI needs to be enabled. The boot script on the host adds 'console=hvc0' so that the full boot output appears in the console program on the host. Link: https://github.com/tenstorrent/opensbi/ Link: https://github.com/tenstorrent/tt-bh-linux Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com> Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
109 lines
2.8 KiB
Plaintext
109 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
// Copyright 2025 Tenstorrent AI ULC
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
compatible = "tenstorrent,blackhole";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
timebase-frequency = <50000000>;
|
|
|
|
cpu@0 {
|
|
compatible = "sifive,x280", "sifive,rocket0", "riscv";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
mmu-type = "riscv,sv57";
|
|
riscv,isa-base = "rv64i";
|
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
|
|
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
|
|
|
|
cpu0_intc: interrupt-controller {
|
|
compatible = "riscv,cpu-intc";
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "sifive,x280", "sifive,rocket0", "riscv";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
mmu-type = "riscv,sv57";
|
|
riscv,isa-base = "rv64i";
|
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
|
|
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
|
|
|
|
cpu1_intc: interrupt-controller {
|
|
compatible = "riscv,cpu-intc";
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
cpu@2 {
|
|
compatible = "sifive,x280", "sifive,rocket0", "riscv";
|
|
device_type = "cpu";
|
|
reg = <2>;
|
|
mmu-type = "riscv,sv57";
|
|
riscv,isa-base = "rv64i";
|
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
|
|
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
|
|
|
|
cpu2_intc: interrupt-controller {
|
|
compatible = "riscv,cpu-intc";
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "sifive,x280", "sifive,rocket0", "riscv";
|
|
device_type = "cpu";
|
|
reg = <3>;
|
|
mmu-type = "riscv,sv57";
|
|
riscv,isa-base = "rv64i";
|
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
|
|
"zifencei", "zfh", "zba", "zbb", "sscofpmf";
|
|
|
|
cpu3_intc: interrupt-controller {
|
|
compatible = "riscv,cpu-intc";
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
clint0: timer@2000000 {
|
|
compatible = "tenstorrent,blackhole-clint", "sifive,clint0";
|
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
|
interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
|
|
<&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
|
|
<&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
|
|
<&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
|
|
};
|
|
|
|
plic0: interrupt-controller@c000000 {
|
|
compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0";
|
|
reg = <0x0 0x0c000000 0x0 0x04000000>;
|
|
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
|
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
|
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
|
<&cpu3_intc 11>, <&cpu3_intc 9>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <0>;
|
|
riscv,ndev = <128>;
|
|
};
|
|
};
|
|
};
|