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DR1V90 is a FPSoC from Anlogic, which features a RISC-V core as the PS
part and 94,464 LUTs for the PL part.
The PS part integrates a Nuclei UX900 RISC-V core with 32KB L1 icache
and 32KB L1 dcache. It also provides two "snps,dw-apb-uart" compatible
UART controllers.
Some basic information of the processor can be obtained by running a
simple application from nuclei-sdk [1]:
-----Nuclei RISC-V CPU Configuration Information-----
MARCHID: 0xc900
MIMPID: 0x20300
ISA: RV64 A B C D F I M P S U
MCFG: TEE ECC ECLIC PLIC PPI ILM DLM ICACHE DCACHE IREGION No-Safety-Mechanism DLEN=VLEN/2
ILM: 256 KB has-ecc
DLM: 256 KB has-ecc
ICACHE: 32 KB(set=256,way=2,lsize=64,ecc=1)
DCACHE: 32 KB(set=256,way=2,lsize=64,ecc=1)
TLB: MainTLB(set=32,way=2,entry=1,ecc=1) ITLB(entry=8) DTLB(entry=8)
IREGION: 0x68000000 128 MB
Unit Size Address
INFO 64KB 0x68000000
DEBUG 64KB 0x68010000
ECLIC 64KB 0x68020000
TIMER 64KB 0x68030000
PLIC 64MB 0x6c000000
INFO-Detail:
mpasize : 0
PPI: 0xf8000000 128 MB
-----End of Nuclei CPU INFO-----
Link: https://github.com/Nuclei-Software/nuclei-sdk/blob/master/application/baremetal/cpuinfo/main.c [1]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
101 lines
2.5 KiB
Plaintext
101 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Anlogic DR1V90";
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compatible = "anlogic,dr1v90";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <800000000>;
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cpu@0 {
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compatible = "nuclei,ux900", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <256>;
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d-cache-size = <32768>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <256>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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reg = <0>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
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"zbkc", "zbs", "zicntr", "zicsr", "zifencei",
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"zihintpause", "zihpm";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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aclint_mswi: interrupt-controller@68031000 {
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compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
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reg = <0x0 0x68031000 0x0 0x4000>;
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interrupts-extended = <&cpu0_intc 3>;
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};
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aclint_mtimer: timer@68035000 {
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compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
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reg = <0x0 0x68035000 0x0 0x8000>;
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reg-names = "mtimecmp";
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interrupts-extended = <&cpu0_intc 7>;
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};
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aclint_sswi: interrupt-controller@6803d000 {
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compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
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reg = <0x0 0x6803d000 0x0 0x3000>;
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#interrupt-cells = <0>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 1>;
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};
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plic: interrupt-controller@6c000000 {
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compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
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reg = <0x0 0x6c000000 0x0 0x4000000>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
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riscv,ndev = <150>;
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};
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uart0: serial@f8400000 {
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compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
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reg = <0x0 0xf8400000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupts = <71>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: serial@f8401000 {
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compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
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reg = <0x0 0xf8401000 0x0 0x1000>;
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clock-frequency = <50000000>;
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interrupts = <72>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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};
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