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c03a37773b
Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, and interrupt controller. Signed-off-by: Albert Yang <yangzh0906@thundersoft.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
98 lines
2.0 KiB
Plaintext
98 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "bst,c1200";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x200>;
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x300>;
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enable-method = "psci";
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next-level-cache = <&l2_cache>;
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};
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l2_cache: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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uart0: serial@20008000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x20008000 0x0 0x1000>;
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clock-frequency = <25000000>;
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interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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gic: interrupt-controller@32800000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x32800000 0x0 0x10000>,
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<0x0 0x32880000 0x0 0x100000>;
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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