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Document the RPMh Network-On-Chip Interconnect in Glymur platform. Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250814-glymur-icc-v2-1-596cca6b6015@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
173 lines
4.4 KiB
YAML
173 lines
4.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR
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maintainers:
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- Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
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description: |
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RPMh interconnect providers support system bandwidth requirements through
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RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
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able to communicate with the BCM through the Resource State Coordinator (RSC)
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associated with each execution environment. Provider nodes must point to at
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least one RPMh device child node pertaining to their RSC and each provider
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can map to multiple RPMh resources.
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See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h
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properties:
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compatible:
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enum:
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- qcom,glymur-aggre1-noc
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- qcom,glymur-aggre2-noc
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- qcom,glymur-aggre3-noc
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- qcom,glymur-aggre4-noc
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- qcom,glymur-clk-virt
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- qcom,glymur-cnoc-cfg
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- qcom,glymur-cnoc-main
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- qcom,glymur-hscnoc
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- qcom,glymur-lpass-ag-noc
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- qcom,glymur-lpass-lpiaon-noc
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- qcom,glymur-lpass-lpicx-noc
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- qcom,glymur-mc-virt
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- qcom,glymur-mmss-noc
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- qcom,glymur-nsinoc
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- qcom,glymur-nsp-noc
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- qcom,glymur-oobm-ss-noc
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- qcom,glymur-pcie-east-anoc
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- qcom,glymur-pcie-east-slv-noc
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- qcom,glymur-pcie-west-anoc
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- qcom,glymur-pcie-west-slv-noc
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- qcom,glymur-system-noc
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 4
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required:
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- compatible
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allOf:
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- $ref: qcom,rpmh-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-clk-virt
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- qcom,glymur-mc-virt
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then:
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properties:
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reg: false
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else:
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required:
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- reg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-pcie-west-anoc
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then:
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properties:
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clocks:
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items:
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- description: aggre PCIE_3A WEST AXI clock
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- description: aggre PCIE_3B WEST AXI clock
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- description: aggre PCIE_4 WEST AXI clock
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- description: aggre PCIE_6 WEST AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-pcie-east-anoc
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then:
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properties:
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clocks:
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items:
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- description: aggre PCIE_5 EAST AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-aggre2-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre USB3 TERT AXI clock
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- description: aggre USB4_2 AXI clock
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- description: aggre UFS PHY AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-aggre4-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre USB3 PRIM AXI clock
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- description: aggre USB3 SEC AXI clock
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- description: aggre USB4_0 AXI clock
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- description: aggre USB4_1 AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,glymur-pcie-west-anoc
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- qcom,glymur-pcie-east-anoc
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- qcom,glymur-aggre2-noc
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- qcom,glymur-aggre4-noc
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then:
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required:
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- clocks
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else:
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properties:
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clocks: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,glymur-gcc.h>
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clk_virt: interconnect-0 {
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compatible = "qcom,glymur-clk-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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aggre1_noc: interconnect@16e0000 {
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compatible = "qcom,glymur-aggre1-noc";
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reg = <0x016e0000 0x14400>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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aggre4_noc: interconnect@1740000 {
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compatible = "qcom,glymur-aggre4-noc";
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reg = <0x01740000 0x14400>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
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<&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
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};
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