Files
linux/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml
Raviteja Laggyshetty 7fdc1d1b02 dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Glymur SoC
Document the RPMh Network-On-Chip Interconnect in Glymur platform.

Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250814-glymur-icc-v2-1-596cca6b6015@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
2025-08-15 00:30:47 +03:00

173 lines
4.4 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR
maintainers:
- Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
description: |
RPMh interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h
properties:
compatible:
enum:
- qcom,glymur-aggre1-noc
- qcom,glymur-aggre2-noc
- qcom,glymur-aggre3-noc
- qcom,glymur-aggre4-noc
- qcom,glymur-clk-virt
- qcom,glymur-cnoc-cfg
- qcom,glymur-cnoc-main
- qcom,glymur-hscnoc
- qcom,glymur-lpass-ag-noc
- qcom,glymur-lpass-lpiaon-noc
- qcom,glymur-lpass-lpicx-noc
- qcom,glymur-mc-virt
- qcom,glymur-mmss-noc
- qcom,glymur-nsinoc
- qcom,glymur-nsp-noc
- qcom,glymur-oobm-ss-noc
- qcom,glymur-pcie-east-anoc
- qcom,glymur-pcie-east-slv-noc
- qcom,glymur-pcie-west-anoc
- qcom,glymur-pcie-west-slv-noc
- qcom,glymur-system-noc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
required:
- compatible
allOf:
- $ref: qcom,rpmh-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-clk-virt
- qcom,glymur-mc-virt
then:
properties:
reg: false
else:
required:
- reg
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-pcie-west-anoc
then:
properties:
clocks:
items:
- description: aggre PCIE_3A WEST AXI clock
- description: aggre PCIE_3B WEST AXI clock
- description: aggre PCIE_4 WEST AXI clock
- description: aggre PCIE_6 WEST AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-pcie-east-anoc
then:
properties:
clocks:
items:
- description: aggre PCIE_5 EAST AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-aggre2-noc
then:
properties:
clocks:
items:
- description: aggre USB3 TERT AXI clock
- description: aggre USB4_2 AXI clock
- description: aggre UFS PHY AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-aggre4-noc
then:
properties:
clocks:
items:
- description: aggre USB3 PRIM AXI clock
- description: aggre USB3 SEC AXI clock
- description: aggre USB4_0 AXI clock
- description: aggre USB4_1 AXI clock
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-pcie-west-anoc
- qcom,glymur-pcie-east-anoc
- qcom,glymur-aggre2-noc
- qcom,glymur-aggre4-noc
then:
required:
- clocks
else:
properties:
clocks: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,glymur-gcc.h>
clk_virt: interconnect-0 {
compatible = "qcom,glymur-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,glymur-aggre1-noc";
reg = <0x016e0000 0x14400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre4_noc: interconnect@1740000 {
compatible = "qcom,glymur-aggre4-noc";
reg = <0x01740000 0x14400>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
<&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
};