Files
linux/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml
Matti Vaittinen d021fb3ae8 dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO
The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can
be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.

The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O
voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with
daisy-chain configuration) and maximum sampling rate is 1MSPS.

Add a device tree binding document for the ROHM BD79112.

Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2025-09-15 20:52:11 +01:00

105 lines
1.9 KiB
YAML

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/rohm,bd79112.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD79112 ADC/GPO
maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
The ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. ADC input pins can be
also configured as general purpose inputs/outputs. SPI should use MODE 3.
properties:
compatible:
const: rohm,bd79112
reg:
maxItems: 1
spi-cpha: true
spi-cpol: true
gpio-controller: true
"#gpio-cells":
const: 2
vdd-supply: true
iovdd-supply: true
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^channel@([0-9]|[12][0-9]|3[01])$":
type: object
$ref: /schemas/iio/adc/adc.yaml#
description: Represents ADC channel. Omitted channels' inputs are GPIOs.
properties:
reg:
description: AIN pin number
minimum: 0
maximum: 31
required:
- reg
additionalProperties: false
required:
- compatible
- reg
- iovdd-supply
- vdd-supply
- spi-cpha
- spi-cpol
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
adc: adc@0 {
compatible = "rohm,bd79112";
reg = <0x0>;
spi-cpha;
spi-cpol;
vdd-supply = <&dummyreg>;
iovdd-supply = <&dummyreg>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
channel@16 {
reg = <16>;
};
channel@20 {
reg = <20>;
};
};
};