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01585d7470
yamllint has gained a new check which checks for inconsistent quoting (mixed " and ' quotes within a file). Fix all the cases yamllint found so we can enable the check (once the check is in a release). As single quotes are (slightly) preferred, use them throughout the modified files even if double quotes are mostly used. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://patch.msgid.link/20251015232015.846282-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
111 lines
2.7 KiB
YAML
111 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Clock and Reset Controller
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maintainers:
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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The Clock and Reset (CAR) is the HW module responsible for muxing and gating
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Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
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CLKGEN provides the registers to program the PLLs. It controls most of
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the clock source programming and most of the clock dividers.
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CLKGEN input signals include the external clock for the reference frequency
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(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
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Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
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RSTGEN provides the registers needed to control resetting of each block in
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the Tegra system.
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properties:
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compatible:
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enum:
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- nvidia,tegra124-car
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- nvidia,tegra132-car
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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nvidia,external-memory-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of the external memory controller node
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patternProperties:
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'^emc-timings-[0-9]+$':
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type: object
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properties:
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nvidia,ram-code:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
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this timing set is used for
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patternProperties:
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'^timing-[0-9]+$':
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type: object
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properties:
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clock-frequency:
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description:
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external memory clock rate in Hz
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minimum: 1000000
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maximum: 1000000000
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nvidia,parent-clock-frequency:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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rate of parent clock in Hz
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minimum: 1000000
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maximum: 1000000000
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clocks:
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items:
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- description: parent clock of EMC
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clock-names:
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items:
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- const: emc-parent
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required:
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- clock-frequency
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- nvidia,parent-clock-frequency
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- clocks
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- clock-names
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra124-car.h>
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car: clock-controller@60006000 {
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compatible = "nvidia,tegra124-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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