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05bd63959a
Disable support for flushing the L1 data cache to mitigate L1TF if CPU mitigations are disabled for the entire kernel. KVM's mitigation of L1TF is in no way special enough to justify ignoring CONFIG_CPU_MITIGATIONS=n. Deliberately use CPU_MITIGATIONS instead of the more precise MITIGATION_L1TF, as MITIGATION_L1TF only controls the default behavior, i.e. CONFIG_MITIGATION_L1TF=n doesn't completely disable L1TF mitigations in the kernel. Keep the vmentry_l1d_flush module param to avoid breaking existing setups, and leverage the .set path to alert the user to the fact that vmentry_l1d_flush will be ignored. Don't bother validating the incoming value; if an admin misconfigures vmentry_l1d_flush, the fact that the bad configuration won't be detected when running with CONFIG_CPU_MITIGATIONS=n is likely the least of their worries. Reviewed-by: Brendan Jackman <jackmanb@google.com> Link: https://patch.msgid.link/20251113233746.1703361-9-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_HARDIRQ_H
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#define _ASM_X86_HARDIRQ_H
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#include <linux/threads.h>
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typedef struct {
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#if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL)
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u8 kvm_cpu_l1tf_flush_l1d;
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#endif
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unsigned int __nmi_count; /* arch dependent */
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#ifdef CONFIG_X86_LOCAL_APIC
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unsigned int apic_timer_irqs; /* arch dependent */
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unsigned int irq_spurious_count;
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unsigned int icr_read_retry_count;
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#endif
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#if IS_ENABLED(CONFIG_KVM)
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unsigned int kvm_posted_intr_ipis;
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unsigned int kvm_posted_intr_wakeup_ipis;
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unsigned int kvm_posted_intr_nested_ipis;
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#endif
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unsigned int x86_platform_ipis; /* arch dependent */
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unsigned int apic_perf_irqs;
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unsigned int apic_irq_work_irqs;
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#ifdef CONFIG_SMP
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unsigned int irq_resched_count;
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unsigned int irq_call_count;
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#endif
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unsigned int irq_tlb_count;
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#ifdef CONFIG_X86_THERMAL_VECTOR
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unsigned int irq_thermal_count;
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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unsigned int irq_threshold_count;
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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unsigned int irq_deferred_error_count;
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#endif
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#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
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unsigned int irq_hv_callback_count;
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#endif
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#if IS_ENABLED(CONFIG_HYPERV)
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unsigned int irq_hv_reenlightenment_count;
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unsigned int hyperv_stimer0_count;
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#endif
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#ifdef CONFIG_X86_POSTED_MSI
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unsigned int posted_msi_notification_count;
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#endif
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} ____cacheline_aligned irq_cpustat_t;
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DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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#ifdef CONFIG_X86_POSTED_MSI
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DECLARE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);
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#endif
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#define __ARCH_IRQ_STAT
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#define inc_irq_stat(member) this_cpu_inc(irq_stat.member)
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extern void ack_bad_irq(unsigned int irq);
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extern u64 arch_irq_stat_cpu(unsigned int cpu);
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#define arch_irq_stat_cpu arch_irq_stat_cpu
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extern u64 arch_irq_stat(void);
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#define arch_irq_stat arch_irq_stat
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DECLARE_PER_CPU_CACHE_HOT(u16, __softirq_pending);
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#define local_softirq_pending_ref __softirq_pending
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#if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL)
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/*
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* This function is called from noinstr interrupt contexts
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* and must be inlined to not get instrumentation.
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*/
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static __always_inline void kvm_set_cpu_l1tf_flush_l1d(void)
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{
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__this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1);
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}
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static __always_inline void kvm_clear_cpu_l1tf_flush_l1d(void)
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{
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__this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 0);
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}
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static __always_inline bool kvm_get_cpu_l1tf_flush_l1d(void)
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{
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return __this_cpu_read(irq_stat.kvm_cpu_l1tf_flush_l1d);
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}
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#else /* !IS_ENABLED(CONFIG_KVM_INTEL) */
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static __always_inline void kvm_set_cpu_l1tf_flush_l1d(void) { }
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#endif /* IS_ENABLED(CONFIG_KVM_INTEL) */
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#endif /* _ASM_X86_HARDIRQ_H */
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