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Most implementations cache the combined result of two-stage translation, but some, like Andes cores, use split TLBs that store VS-stage and G-stage entries separately. On such systems, when a VCPU migrates to another CPU, an additional HFENCE.VVMA is required to avoid using stale VS-stage entries, which could otherwise cause guest faults. Introduce a static key to identify CPUs with split two-stage TLBs. When enabled, KVM issues an extra HFENCE.VVMA on VCPU migration to prevent stale VS-stage mappings. Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://lore.kernel.org/r/20251117084555.157642-1-minachou@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
27 lines
654 B
C
27 lines
654 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 Ventana Micro Systems Inc.
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*/
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#ifndef __RISCV_KVM_VMID_H_
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#define __RISCV_KVM_VMID_H_
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#include <linux/kvm_types.h>
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struct kvm_vmid {
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/*
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* Writes to vmid_version and vmid happen with vmid_lock held
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* whereas reads happen without any lock held.
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*/
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unsigned long vmid_version;
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unsigned long vmid;
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};
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void __init kvm_riscv_gstage_vmid_detect(void);
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unsigned long kvm_riscv_gstage_vmid_bits(void);
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int kvm_riscv_gstage_vmid_init(struct kvm *kvm);
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bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid);
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void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu);
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#endif
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