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Most implementations cache the combined result of two-stage translation, but some, like Andes cores, use split TLBs that store VS-stage and G-stage entries separately. On such systems, when a VCPU migrates to another CPU, an additional HFENCE.VVMA is required to avoid using stale VS-stage entries, which could otherwise cause guest faults. Introduce a static key to identify CPUs with split two-stage TLBs. When enabled, KVM issues an extra HFENCE.VVMA on VCPU migration to prevent stale VS-stage mappings. Signed-off-by: Hui Min Mina Chou <minachou@andestech.com> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Link: https://lore.kernel.org/r/20251117084555.157642-1-minachou@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 Ventana Micro Systems Inc.
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*/
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#ifndef __RISCV_KVM_TLB_H_
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#define __RISCV_KVM_TLB_H_
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#include <linux/kvm_types.h>
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enum kvm_riscv_hfence_type {
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KVM_RISCV_HFENCE_UNKNOWN = 0,
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KVM_RISCV_HFENCE_GVMA_VMID_GPA,
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KVM_RISCV_HFENCE_GVMA_VMID_ALL,
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KVM_RISCV_HFENCE_VVMA_ASID_GVA,
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KVM_RISCV_HFENCE_VVMA_ASID_ALL,
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KVM_RISCV_HFENCE_VVMA_GVA,
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KVM_RISCV_HFENCE_VVMA_ALL
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};
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struct kvm_riscv_hfence {
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enum kvm_riscv_hfence_type type;
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unsigned long asid;
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unsigned long vmid;
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unsigned long order;
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gpa_t addr;
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gpa_t size;
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};
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#define KVM_RISCV_VCPU_MAX_HFENCE 64
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#define KVM_RISCV_GSTAGE_TLB_MIN_ORDER 12
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void kvm_riscv_local_hfence_gvma_vmid_gpa(unsigned long vmid,
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gpa_t gpa, gpa_t gpsz,
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unsigned long order);
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void kvm_riscv_local_hfence_gvma_vmid_all(unsigned long vmid);
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void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz,
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unsigned long order);
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void kvm_riscv_local_hfence_gvma_all(void);
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void kvm_riscv_local_hfence_vvma_asid_gva(unsigned long vmid,
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unsigned long asid,
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unsigned long gva,
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unsigned long gvsz,
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unsigned long order);
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void kvm_riscv_local_hfence_vvma_asid_all(unsigned long vmid,
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unsigned long asid);
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void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid,
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unsigned long gva, unsigned long gvsz,
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unsigned long order);
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void kvm_riscv_local_hfence_vvma_all(unsigned long vmid);
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void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu);
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void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu);
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void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu);
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void kvm_riscv_hfence_vvma_all_process(struct kvm_vcpu *vcpu);
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void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu);
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void kvm_riscv_fence_i(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask);
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void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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gpa_t gpa, gpa_t gpsz,
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unsigned long order, unsigned long vmid);
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void kvm_riscv_hfence_gvma_vmid_all(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long vmid);
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void kvm_riscv_hfence_vvma_asid_gva(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long gva, unsigned long gvsz,
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unsigned long order, unsigned long asid,
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unsigned long vmid);
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void kvm_riscv_hfence_vvma_asid_all(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long asid, unsigned long vmid);
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void kvm_riscv_hfence_vvma_gva(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long gva, unsigned long gvsz,
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unsigned long order, unsigned long vmid);
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void kvm_riscv_hfence_vvma_all(struct kvm *kvm,
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unsigned long hbase, unsigned long hmask,
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unsigned long vmid);
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#endif
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