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e6ab504633
Move the gpib drivers out of staging and into the "real" part of the kernel. This entails: - Remove the gpib Kconfig menu and Makefile build rule from staging. - Remove gpib/uapi from the header file search path in subdir-ccflags of the gpib Makefile - move the gpib/uapi files to include/uapi/linux - Move the gpib tree out of staging to drivers. - Remove the word "Linux" from the gpib Kconfig file. - Add the gpib Kconfig menu and Makefile build rule to drivers Signed-off-by: Dave Penkler <dpenkler@gmail.com> Link: https://patch.msgid.link/20251117144021.23569-5-dpenkler@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
235 lines
6.0 KiB
C
235 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Hardware driver for NI Mite PCI interface chip
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*
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* Copyright (C) 1999 David A. Schleef <ds@stm.lbl.gov>
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*/
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#ifndef _MITE_H_
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#define _MITE_H_
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#include <linux/pci.h>
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#define PCI_VENDOR_ID_NATINST 0x1093
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//#define DEBUG_MITE
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#ifdef DEBUG_MITE
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#define MDPRINTK(format, args...) pr_debug(format, ## args)
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#else
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#define MDPRINTK(args...)
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#endif
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#define MITE_RING_SIZE 3000
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struct mite_dma_chain {
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u32 count;
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u32 addr;
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u32 next;
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};
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struct mite_struct {
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struct mite_struct *next;
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int used;
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struct pci_dev *pcidev;
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unsigned long mite_phys_addr;
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void __iomem *mite_io_addr;
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unsigned long daq_phys_addr;
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void __iomem *daq_io_addr;
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int DMA_CheckNearEnd;
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struct mite_dma_chain ring[MITE_RING_SIZE];
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};
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extern struct mite_struct *mite_devices;
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extern inline unsigned int mite_irq(struct mite_struct *mite)
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{
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return mite->pcidev->irq;
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};
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extern inline unsigned int mite_device_id(struct mite_struct *mite)
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{
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return mite->pcidev->device;
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};
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void mite_init(void);
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void mite_cleanup(void);
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int mite_setup(struct mite_struct *mite);
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void mite_unsetup(struct mite_struct *mite);
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void mite_list_devices(void);
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#define CHAN_OFFSET(x) (0x100 * (x))
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/* DMA base for chan 0 is 0x500, chan 1 is 0x600 */
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#define MITE_CHOR 0x500
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#define CHOR_DMARESET BIT(31)
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#define CHOR_SET_SEND_TC BIT(11)
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#define CHOR_CLR_SEND_TC BIT(10)
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#define CHOR_SET_LPAUSE BIT(9)
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#define CHOR_CLR_LPAUSE BIT(8)
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#define CHOR_CLRDONE BIT(7)
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#define CHOR_CLRRB BIT(6)
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#define CHOR_CLRLC BIT(5)
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#define CHOR_FRESET BIT(4)
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#define CHOR_ABORT BIT(3)
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#define CHOR_STOP BIT(2)
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#define CHOR_CONT BIT(1)
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#define CHOR_START BIT(0)
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#define CHOR_PON (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE)
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#define MITE_CHCR 0x504
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#define CHCR_SET_DMA_IE BIT(31)
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#define CHCR_CLR_DMA_IE BIT(30)
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#define CHCR_SET_LINKP_IE BIT(29)
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#define CHCR_CLR_LINKP_IE BIT(28)
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#define CHCR_SET_SAR_IE BIT(27)
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#define CHCR_CLR_SAR_IE BIT(26)
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#define CHCR_SET_DONE_IE BIT(25)
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#define CHCR_CLR_DONE_IE BIT(24)
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#define CHCR_SET_MRDY_IE BIT(23)
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#define CHCR_CLR_MRDY_IE BIT(22)
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#define CHCR_SET_DRDY_IE BIT(21)
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#define CHCR_CLR_DRDY_IE BIT(20)
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#define CHCR_SET_LC_IE BIT(19)
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#define CHCR_CLR_LC_IE BIT(18)
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#define CHCR_SET_CONT_RB_IE BIT(17)
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#define CHCR_CLR_CONT_RB_IE BIT(16)
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#define CHCR_FIFODIS BIT(15)
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#define CHCR_FIFO_ON 0
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#define CHCR_BURSTEN BIT(14)
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#define CHCR_NO_BURSTEN 0
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#define CHCR_NFTP(x) ((x) << 11)
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#define CHCR_NFTP0 CHCR_NFTP(0)
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#define CHCR_NFTP1 CHCR_NFTP(1)
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#define CHCR_NFTP2 CHCR_NFTP(2)
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#define CHCR_NFTP4 CHCR_NFTP(3)
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#define CHCR_NFTP8 CHCR_NFTP(4)
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#define CHCR_NFTP16 CHCR_NFTP(5)
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#define CHCR_NETP(x) ((x) << 11)
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#define CHCR_NETP0 CHCR_NETP(0)
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#define CHCR_NETP1 CHCR_NETP(1)
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#define CHCR_NETP2 CHCR_NETP(2)
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#define CHCR_NETP4 CHCR_NETP(3)
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#define CHCR_NETP8 CHCR_NETP(4)
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#define CHCR_CHEND1 BIT(5)
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#define CHCR_CHEND0 BIT(4)
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#define CHCR_DIR BIT(3)
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#define CHCR_DEV_TO_MEM CHCR_DIR
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#define CHCR_MEM_TO_DEV 0
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#define CHCR_NORMAL ((0) << 0)
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#define CHCR_CONTINUE ((1) << 0)
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#define CHCR_RINGBUFF ((2) << 0)
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#define CHCR_LINKSHORT ((4) << 0)
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#define CHCR_LINKLONG ((5) << 0)
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#define CHCRPON (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | \
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CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE | \
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CHCR_CLR_LC_IE | CHCR_CLR_CONT_IE)
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#define MITE_TCR 0x508
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/* CR bits */
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#define CR_RL(x) ((x) << 21)
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#define CR_RL0 CR_RL(0)
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#define CR_RL1 CR_RL(1)
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#define CR_RL2 CR_RL(2)
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#define CR_RL4 CR_RL(3)
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#define CR_RL8 CR_RL(4)
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#define CR_RL16 CR_RL(5)
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#define CR_RL32 CR_RL(6)
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#define CR_RL64 CR_RL(7)
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#define CR_RD(x) ((x) << 19)
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#define CR_RD0 CR_RD(0)
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#define CR_RD32 CR_RD(1)
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#define CR_RD512 CR_RD(2)
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#define CR_RD8192 CR_RD(3)
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#define CR_REQS(x) ((x) << 16)
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#define CR_REQSDRQ0 CR_REQS(4)
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#define CR_REQSDRQ1 CR_REQS(5)
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#define CR_REQSDRQ2 CR_REQS(6)
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#define CR_REQSDRQ3 CR_REQS(7)
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#define CR_ASEQX(x) ((x) << 10)
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#define CR_ASEQX0 CR_ASEQX(0)
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#define CR_ASEQDONT CR_ASEQX0
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#define CR_ASEQXP1 CR_ASEQX(1)
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#define CR_ASEQUP CR_ASEQXP1
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#define CR_ASEQXP2 CR_ASEQX(2)
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#define CR_ASEQDOWN CR_ASEQXP2
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#define CR_ASEQXP4 CR_ASEQX(3)
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#define CR_ASEQXP8 CR_ASEQX(4)
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#define CR_ASEQXP16 CR_ASEQX(5)
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#define CR_ASEQXP32 CR_ASEQX(6)
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#define CR_ASEQXP64 CR_ASEQX(7)
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#define CR_ASEQXM1 CR_ASEQX(9)
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#define CR_ASEQXM2 CR_ASEQX(10)
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#define CR_ASEQXM4 CR_ASEQX(11)
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#define CR_ASEQXM8 CR_ASEQX(12)
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#define CR_ASEQXM16 CR_ASEQX(13)
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#define CR_ASEQXM32 CR_ASEQX(14)
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#define CR_ASEQXM64 CR_ASEQX(15)
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#define CR_PSIZEBYTE BIT(8)
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#define CR_PSIZEHALF (2 << 8)
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#define CR_PSIZEWORD (3 << 8)
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#define CR_PORTCPU (0 << 6)
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#define CR_PORTIO BIT(6)
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#define CR_PORTVXI (2 << 6)
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#define CR_PORTMXI (3 << 6)
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#define CR_AMDEVICE BIT(0)
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#define CHSR_INT 0x80000000
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#define CHSR_DONE 0x02000000
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#define CHSR_LINKC 0x00080000
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#define MITE_MCR 0x50c
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#define MCRPON 0
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#define MITE_MAR 0x510
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#define MITE_DCR 0x514
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#define DCR_NORMAL BIT(29)
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#define DCRPON 0
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#define MITE_DAR 0x518
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#define MITE_LKCR 0x51c
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#define MITE_LKAR 0x520
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#define MITE_LLKAR 0x524
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#define MITE_BAR 0x528
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#define MITE_BCR 0x52c
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#define MITE_SAR 0x530
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#define MITE_WSCR 0x534
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#define MITE_WSER 0x538
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#define MITE_CHSR 0x53c
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#define MITE_FCR 0x540
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#define MITE_FIFO 0x80
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#define MITE_FIFOEND 0xff
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#define MITE_AMRAM 0x00
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#define MITE_AMDEVICE 0x01
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#define MITE_AMHOST_A32_SINGLE 0x09
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#define MITE_AMHOST_A24_SINGLE 0x39
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#define MITE_AMHOST_A16_SINGLE 0x29
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#define MITE_AMHOST_A32_BLOCK 0x0b
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#define MITE_AMHOST_A32D64_BLOCK 0x08
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#define MITE_AMHOST_A24_BLOCK 0x3b
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enum mite_registers {
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MITE_IODWBSR = 0xc0, // IO Device Window Base Size Register
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MITE_CSIGR = 0x460, // chip signature
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MITE_IODWBSR_1 = 0xc4, // IO Device Window Base Size Register 1 (used by 6602 boards)
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MITE_IODWCR_1 = 0xf4
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};
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enum MITE_IODWBSR_bits {
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WENAB = 0x80, // window enable
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WENAB_6602 = 0x8c // window enable for 6602 boards
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};
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#endif
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