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20eee0f69c
The Renesas USB PHY hardware block needs to have the PWRRDY bit in the system controller set before applying any other settings. The PWRRDY bit must be controlled during power-on, power-off, and system suspend/resume sequences as follows: - during power-on/resume, it must be set to zero before enabling clocks and modules - during power-off/suspend, it must be set to one after disabling clocks and modules Add the renesas,sysc-pwrrdy device tree property, which allows the reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system controller PWRRDY bit at the appropriate time. Along with it add a new compatible for the RZ/G3S SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
107 lines
2.6 KiB
YAML
107 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G2L,V2L} USBPHY Control
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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description:
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The RZ/G2L USBPHY Control mainly controls reset and power down of the
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USB/PHY.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
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- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
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- renesas,r9a07g054-usbphy-ctrl # RZ/V2L
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- const: renesas,rzg2l-usbphy-ctrl
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- const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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'#reset-cells':
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const: 1
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description: |
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The phandle's argument in the reset specifier is the PHY reset associated
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with the USB port.
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0 = Port 1 Phy reset
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1 = Port 2 Phy reset
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regulator-vbus:
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type: object
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description: USB VBUS regulator
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$ref: /schemas/regulator/regulator.yaml#
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unevaluatedProperties: false
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renesas,sysc-pwrrdy:
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description:
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The system controller PWRRDY indicates to the USB PHY if the power supply
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is ready. PWRRDY needs to be set during power-on before applying any
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other settings. It also needs to be set before powering off the USB.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description:
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System controller phandle required by USB PHY CTRL driver to set
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PWRRDY
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- description: Register offset associated with PWRRDY
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- description: Register bitmask associated with PWRRDY
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required:
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- compatible
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- reg
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- clocks
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- resets
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- power-domains
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- '#reset-cells'
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- regulator-vbus
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g045-usbphy-ctrl
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then:
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required:
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- renesas,sysc-pwrrdy
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else:
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properties:
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renesas,sysc-pwrrdy: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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phyrst: usbphy-ctrl@11c40000 {
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compatible = "renesas,r9a07g044-usbphy-ctrl",
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"renesas,rzg2l-usbphy-ctrl";
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reg = <0x11c40000 0x10000>;
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clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
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resets = <&cpg R9A07G044_USB_PRESETN>;
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power-domains = <&cpg>;
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#reset-cells = <1>;
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regulator-vbus {
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regulator-name = "vbus";
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};
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};
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