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208eed95fc
Pull SoC driver updates from Arnd Bergmann:
"This is the first half of the driver changes:
- A treewide interface change to the "syscore" operations for power
management, as a preparation for future Tegra specific changes
- Reset controller updates with added drivers for LAN969x, eic770 and
RZ/G3S SoCs
- Protection of system controller registers on Renesas and Google
SoCs, to prevent trivially triggering a system crash from e.g.
debugfs access
- soc_device identification updates on Nvidia, Exynos and Mediatek
- debugfs support in the ST STM32 firewall driver
- Minor updates for SoC drivers on AMD/Xilinx, Renesas, Allwinner, TI
- Cleanups for memory controller support on Nvidia and Renesas"
* tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (114 commits)
memory: tegra186-emc: Fix missing put_bpmp
Documentation: reset: Remove reset_controller_add_lookup()
reset: fix BIT macro reference
reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
reset: th1520: Support reset controllers in more subsystems
reset: th1520: Prepare for supporting multiple controllers
dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
reset: remove legacy reset lookup code
clk: davinci: psc: drop unused reset lookup
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: eswin: Add eic7700 reset driver
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: sparx5: add LAN969x support
dt-bindings: reset: microchip: Add LAN969x support
soc: rockchip: grf: Add select correct PWM implementation on RK3368
soc/tegra: pmc: Add USB wake events for Tegra234
amba: tegra-ahb: Fix device leak on SMMU enable
...
110 lines
3.0 KiB
YAML
110 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32 Resource isolation framework security controller
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maintainers:
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- Gatien Chevallier <gatien.chevallier@foss.st.com>
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description: |
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Resource isolation framework (RIF) is a comprehensive set of hardware blocks
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designed to enforce and manage isolation of STM32 hardware resources like
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memory and peripherals.
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The RIFSC (RIF security controller) is composed of three sets of registers,
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each managing a specific set of hardware resources:
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- RISC registers associated with RISUP logic (resource isolation device unit
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for peripherals), assign all non-RIF aware peripherals to zero, one or
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any security domains (secure, privilege, compartment).
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- RIMC registers: associated with RIMU logic (resource isolation master
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unit), assign all non RIF-aware bus master to one security domain by
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setting secure, privileged and compartment information on the system bus.
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Alternatively, the RISUP logic controlling the device port access to a
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peripheral can assign target bus attributes to this peripheral master port
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(supported attribute: CID).
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- RISC registers associated with RISAL logic (resource isolation device unit
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for address space - Lite version), assign address space subregions to one
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security domains (secure, privilege, compartment).
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select:
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properties:
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compatible:
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contains:
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enum:
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- st,stm32mp21-rifsc
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- st,stm32mp25-rifsc
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- st,stm32mp21-rifsc
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- st,stm32mp25-rifsc
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- const: simple-bus
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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"#access-controller-cells":
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const: 1
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description:
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Contains the firewall ID associated to the peripheral.
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patternProperties:
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"@[0-9a-f]+$":
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description: Peripherals
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type: object
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additionalProperties: true
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required:
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- access-controllers
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- "#access-controller-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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// In this example, the usart2 device refers to rifsc as its domain
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// controller.
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// Access rights are verified before creating devices.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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rifsc: bus@42080000 {
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compatible = "st,stm32mp25-rifsc", "simple-bus";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#access-controller-cells = <1>;
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ranges;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ck_flexgen_08>;
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access-controllers = <&rifsc 32>;
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};
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};
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