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41ab5e1625
RISC-V cache drivers for v6.8 The SiFive composable cache driver moves to the cache driver subdirectory from the drivers/soc and grows support for non-coherent cache operations. The immediate user for these is the jh7100 SoC, that a rake of people have on VisionFive v1 or Beagle-V Starlight boards. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP riscv: errata: Add StarFive JH7100 errata soc: sifive: ccache: Add StarFive JH7100 support dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible soc: sifive: shunt ccache driver to drivers/cache Link: https://lore.kernel.org/r/20231221-catatonic-monday-d4c61283b136@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>