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Document the SATA AHCI controller on the EIC7700 SoC platform, including descriptions of its hardware configurations. Signed-off-by: Yulin Lu <luyulin@eswincomputing.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Niklas Cassel <cassel@kernel.org>
80 lines
1.5 KiB
YAML
80 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Eswin EIC7700 SoC SATA Controller
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maintainers:
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- Yulin Lu <luyulin@eswincomputing.com>
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- Huan He <hehuan1@eswincomputing.com>
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description:
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AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI
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SATA v5.00a IP core.
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select:
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properties:
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compatible:
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const: eswin,eic7700-ahci
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required:
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- compatible
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allOf:
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- $ref: snps,dwc-ahci-common.yaml#
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properties:
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compatible:
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items:
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- const: eswin,eic7700-ahci
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- const: snps,dwc-ahci
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: pclk
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- const: aclk
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resets:
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maxItems: 1
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reset-names:
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const: arst
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ports-implemented:
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- reset-names
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- phys
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- phy-names
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- ports-implemented
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unevaluatedProperties: false
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examples:
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- |
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sata@50420000 {
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compatible = "eswin,eic7700-ahci", "snps,dwc-ahci";
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reg = <0x50420000 0x10000>;
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interrupt-parent = <&plic>;
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interrupts = <58>;
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clocks = <&clock 171>, <&clock 186>;
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clock-names = "pclk", "aclk";
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phys = <&sata_phy>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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resets = <&reset 96>;
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reset-names = "arst";
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};
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