Files
linux/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
Alexandre Belloni 84a7f564fa mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
Ocelot PCB123 has a SPI NOR connected on its SPI bus.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20103/
Cc: Mark Brown <broonie@kernel.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Allan Nielsen <allan.nielsen@microsemi.com>
2018-07-31 10:34:34 -07:00

58 lines
691 B
Plaintext

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2017 Microsemi Corporation */
/dts-v1/;
#include "ocelot.dtsi"
/ {
compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0e000000>;
};
};
&uart0 {
status = "okay";
};
&uart2 {
status = "okay";
};
&spi {
status = "okay";
flash@0 {
compatible = "macronix,mx25l25635f", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&mdio0 {
status = "okay";
};
&port0 {
phy-handle = <&phy0>;
};
&port1 {
phy-handle = <&phy1>;
};
&port2 {
phy-handle = <&phy2>;
};
&port3 {
phy-handle = <&phy3>;
};