Thierry Reding a97fbc3ee3 syscore: Pass context data to callbacks ...

Several drivers can benefit from registering per-instance data along
with the syscore operations. To achieve this, move the modifiable fields
out of the syscore_ops structure and into a separate struct syscore that
can be registered with the framework. Add a void * driver data field for
drivers to store contextual data that will be passed to the syscore ops.

Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

2025-11-14 10:01:52 +01:00

..

clk-audio-sync.c

clk: tegra: audio-sync: convert from round_rate() to determine_rate()

2025-09-08 12:50:34 -04:00

clk-bpmp.c

clk: tegra: do not overallocate memory for bpmp clocks

2025-09-21 13:09:12 -07:00

clk-device.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

clk-dfll.c

clk: tegra: Remove redundant semicolons

2025-08-14 13:25:25 -07:00

clk-dfll.h

clk: tegra: clk-dfll: Add suspend and resume support

2019-11-11 14:53:03 +01:00

clk-divider.c

clk: tegra: divider: convert from round_rate() to determine_rate()

2025-09-08 12:50:38 -04:00

clk-id.h

clk: tegra: Fix duplicated SE clock entry

2020-12-10 12:51:59 -08:00

clk-periph-fixed.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-periph-gate.c

clk: tegra: Don't deassert reset on enabling clocks

2021-05-31 15:16:46 +02:00

clk-periph.c

clk: tegra: periph: divider: convert from round_rate() to determine_rate()

2025-09-08 12:50:41 -04:00

clk-pll-out.c

clk: tegra: pllout: Save and restore pllout context

2019-11-11 14:53:02 +01:00

clk-pll.c

clk: tegra: pll: convert from round_rate() to determine_rate()

2025-09-08 12:50:44 -04:00

clk-sdmmc-mux.c

clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops

2021-07-27 14:54:19 -07:00

clk-super.c

clk: tegra: super: convert from round_rate() to determine_rate()

2025-09-08 12:50:47 -04:00

clk-tegra20-emc.c

clk: tegra: Export Tegra20 EMC kernel symbols

2020-11-06 19:24:04 +01:00

clk-tegra20.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

clk-tegra30.c

dt-bindings: clock: tegra30: Add IDs for CSI pad clocks

2025-09-11 18:03:10 +02:00

clk-tegra114.c

clk: tegra: Add DFLL DVCO reset control for Tegra114

2025-09-11 18:29:48 +02:00

clk-tegra124-dfll-fcpu.c

clk: tegra: dfll: Add CVB tables for Tegra114

2025-09-14 08:23:28 +02:00

clk-tegra124-emc.c

clk: tegra: tegra124-emc: Fix potential memory leak

2023-06-14 18:25:51 -07:00

clk-tegra124.c

clk: tegra: Fix Tegra PWM parent clock

2022-10-14 13:44:24 -07:00

clk-tegra210-emc.c

clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()

2025-09-08 12:50:51 -04:00

clk-tegra210.c

syscore: Pass context data to callbacks

2025-11-14 10:01:52 +01:00

clk-tegra-audio.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-tegra-fixed.c

clk: tegra: Remove CLK_M_DIV fixed clocks

2020-03-12 11:33:32 +01:00

clk-tegra-periph.c

clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock

2021-08-11 11:57:01 +02:00

clk-tegra-super-cclk.c

clk: tegra: Avoid calling an uninitialized function

2023-07-04 08:54:37 -07:00

clk-tegra-super-gen4.c

clk: tegra: clk-super: Fix to enable PLLP branches to CPU

2019-11-11 14:53:03 +01:00

clk-utils.c

clk: tegra: Refactor fractional divider calculation

2018-07-25 13:43:34 -07:00

clk.c

Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next

2023-08-30 14:38:19 -07:00

clk.h

clk: tegra: Add DFLL DVCO reset control for Tegra114

2025-09-11 18:29:48 +02:00

cvb.c

clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param

2021-02-11 11:56:05 -08:00

cvb.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

2019-05-30 11:26:41 -07:00

Kconfig

clk: tegra: dfll: Add CVB tables for Tegra114

2025-09-14 08:23:28 +02:00

Makefile

clk: tegra: Support runtime PM and power domain

2021-12-15 18:55:21 +01:00