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d7c001bd76
Factorize the probe function of the mmio based amlogic clock controllers using the newly introduced probe helper. This removes a fair amount of duplicated code. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-3-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
113 lines
2.4 KiB
C
113 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Amlogic Meson8 DDR clock controller
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*
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* Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <dt-bindings/clock/meson8-ddr-clkc.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "meson-clkc-utils.h"
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#define AM_DDR_PLL_CNTL 0x00
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#define AM_DDR_PLL_CNTL1 0x04
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#define AM_DDR_PLL_CNTL2 0x08
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#define AM_DDR_PLL_CNTL3 0x0c
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#define AM_DDR_PLL_CNTL4 0x10
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#define AM_DDR_PLL_STS 0x14
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#define DDR_CLK_CNTL 0x18
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#define DDR_CLK_STS 0x1c
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static struct clk_regmap meson8_ddr_pll_dco = {
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.data = &(struct meson_clk_pll_data){
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.en = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 30,
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.width = 1,
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},
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.m = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 0,
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.width = 9,
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},
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.n = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 9,
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.width = 5,
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},
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.l = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 31,
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.width = 1,
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},
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.rst = {
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.reg_off = AM_DDR_PLL_CNTL,
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.shift = 29,
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.width = 1,
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},
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},
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.hw.init = &(struct clk_init_data){
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.name = "ddr_pll_dco",
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.ops = &meson_clk_pll_ro_ops,
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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static struct clk_regmap meson8_ddr_pll = {
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.data = &(struct clk_regmap_div_data){
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.offset = AM_DDR_PLL_CNTL,
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.shift = 16,
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.width = 2,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "ddr_pll",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&meson8_ddr_pll_dco.hw
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},
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.num_parents = 1,
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},
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};
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static struct clk_hw *meson8_ddr_hw_clks[] = {
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[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
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[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
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};
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static const struct meson_clkc_data meson8_ddr_clkc_data = {
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.hw_clks = {
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.hws = meson8_ddr_hw_clks,
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.num = ARRAY_SIZE(meson8_ddr_hw_clks),
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},
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};
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static const struct of_device_id meson8_ddr_clkc_match_table[] = {
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{
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.compatible = "amlogic,meson8-ddr-clkc",
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.data = &meson8_ddr_clkc_data,
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}, {
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.compatible = "amlogic,meson8b-ddr-clkc",
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.data = &meson8_ddr_clkc_data,
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},
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{ /* sentinel */ }
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};
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static struct platform_driver meson8_ddr_clkc_driver = {
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.probe = meson_clkc_mmio_probe,
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.driver = {
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.name = "meson8-ddr-clkc",
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.of_match_table = meson8_ddr_clkc_match_table,
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},
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};
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builtin_platform_driver(meson8_ddr_clkc_driver);
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